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| author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:24:23 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 166da650a3c864b31193ade893ed99e547c67644 (patch) | |
| tree | 84236bf28007885e864e885fab8e715e332affa6 /src/arch/arm/isa/templates | |
| parent | 00da08902918da13fccc3f2266b7b2f5d0080708 (diff) | |
| download | gem5-166da650a3c864b31193ade893ed99e547c67644.tar.xz | |
arch: ISA parser additions of vector registers
Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.
Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.
Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/templates')
| -rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 10 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 6 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 51f598f50..a0942d151 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010, 2012, 2014 ARM Limited +// Copyright (c) 2010, 2012, 2014, 2016 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -1150,7 +1150,7 @@ def template LoadRegConstructor {{ #if %(use_uops)d assert(numMicroops >= 2); uops = new StaticInstPtr[numMicroops]; - if (_dest == INTREG_PC && !isFloating()) { + if (_dest == INTREG_PC && !isFloating() && !isVector()) { IntRegIndex wbIndexReg = index; uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, _shiftAmt, _shiftType, _index); @@ -1187,7 +1187,7 @@ def template LoadRegConstructor {{ } #else - if (_dest == INTREG_PC && !isFloating()) { + if (_dest == INTREG_PC && !isFloating() && !isVector()) { flags[IsControl] = true; flags[IsIndirectControl] = true; if (conditional) @@ -1216,7 +1216,7 @@ def template LoadImmConstructor {{ #if %(use_uops)d assert(numMicroops >= 2); uops = new StaticInstPtr[numMicroops]; - if (_dest == INTREG_PC && !isFloating()) { + if (_dest == INTREG_PC && !isFloating() && !isVector()) { uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, _imm); uops[0]->setDelayedCommit(); @@ -1250,7 +1250,7 @@ def template LoadImmConstructor {{ uops[1]->setLastMicroop(); } #else - if (_dest == INTREG_PC && !isFloating()) { + if (_dest == INTREG_PC && !isFloating() && !isVector()) { flags[IsControl] = true; flags[IsIndirectControl] = true; if (conditional) diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 752ab8d1e..7b372bdee 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010, 2016 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -77,7 +77,7 @@ def template DataImmConstructor {{ } } - if (%(is_branch)s && !isFloating()){ + if (%(is_branch)s && !isFloating() && !isVector()){ flags[IsControl] = true; flags[IsIndirectControl] = true; if (condCode == COND_AL || condCode == COND_UC) @@ -117,7 +117,7 @@ def template DataRegConstructor {{ } } - if (%(is_branch)s && !isFloating()){ + if (%(is_branch)s && !isFloating() && !isVector()){ flags[IsControl] = true; flags[IsIndirectControl] = true; if (condCode == COND_AL || condCode == COND_UC) |