ARM: Fix VFP enabled checks for mem instructions

2 files changed, 25 insertions, 2 deletions

diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index 20c1d26b8..0e592c6e4 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -37,6 +37,14 @@
 //
 // Authors: Gabe Black
 
+let {{
+    simdEnabledCheckCode = '''
+        if (!neonEnabled(Cpacr, Cpsr, Fpexc))
+            return disabledFault();
+    '''
+}};
+
+
 def template NeonRegRegRegOpDeclare {{
 template <class _Element>
 class %(class_name)s : public %(base_class)s
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index 5de52738c..8ccfedd0d 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -43,9 +43,24 @@ let {{
             return disabledFault();
     '''
 
-    vmsrrsEnabledCheckCode = '''
+    vmsrEnabledCheckCode = '''
         if (!vfpEnabled(Cpacr, Cpsr))
-            return disabledFault();
+            if (dest != (int)MISCREG_FPEXC && dest != (int)MISCREG_FPSID)
+                return disabledFault();
+        if (!inPrivilegedMode(Cpsr))
+            if (dest != (int)MISCREG_FPSCR)
+                return disabledFault();
+
+    '''
+
+    vmrsEnabledCheckCode = '''
+        if (!vfpEnabled(Cpacr, Cpsr))
+            if (op1 != (int)MISCREG_FPEXC && op1 != (int)MISCREG_FPSID &&
+                op1 != (int)MISCREG_MVFR0 && op1 != (int)MISCREG_MVFR1)
+                return disabledFault();
+        if (!inPrivilegedMode(Cpsr))
+            if (op1 != (int)MISCREG_FPSCR)
+                return disabledFault();
     '''
 }};