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authorAli Saidi <Ali.Saidi@ARM.com>2011-05-13 17:27:01 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-05-13 17:27:01 -0500
commit2178859b76bb13b1d225fc4dffa04d43d2db2e14 (patch)
treec57a005891e10565c9e7552cb90037a667001807 /src/arch/arm/isa/templates
parent4bf48a11efd7253bdb7a61da42d2bc754033757b (diff)
downloadgem5-2178859b76bb13b1d225fc4dffa04d43d2db2e14.tar.xz
ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags.
Diffstat (limited to 'src/arch/arm/isa/templates')
-rw-r--r--src/arch/arm/isa/templates/pred.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 4ab1335e0..a0f811f6d 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -46,8 +46,8 @@
//
let {{
- predicateTest = 'testPredicate(OptCondCodes, condCode)'
- condPredicateTest = 'testPredicate(CondCodes, condCode)'
+ predicateTest = 'testPredicate(OptCondCodesF, condCode)'
+ condPredicateTest = 'testPredicate(CondCodesF, condCode)'
}};
def template DataImmDeclare {{