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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
| tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/templates | |
| parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
| download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz | |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/templates')
| -rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/vfp.isa | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index a0f811f6d..04f253ca9 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -46,8 +46,8 @@ // let {{ - predicateTest = 'testPredicate(OptCondCodesF, condCode)' - condPredicateTest = 'testPredicate(CondCodesF, condCode)' + predicateTest = 'testPredicate(OptCondCodesNZ, OptCondCodesC, OptCondCodesV, condCode)' + condPredicateTest = 'testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)' }}; def template DataImmDeclare {{ diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index 8888dc0ae..90dd751ff 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -62,6 +62,10 @@ let {{ if (op1 != (int)MISCREG_FPSCR) return disabledFault(); ''' + vmrsApsrEnabledCheckCode = ''' + if (!vfpEnabled(Cpacr, Cpsr)) + return disabledFault(); + ''' }}; def template FpRegRegOpDeclare {{ |