ARM: Identify branches as conditional or unconditional and direct or indirect.

1 files changed, 37 insertions, 0 deletions

diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index d1f581f51..6abf76963 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -57,7 +57,11 @@ def template BranchImmConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
+
     }
 }};
 
@@ -69,6 +73,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, int32_t _imm,
                        ConditionCode _condCode);
         %(BasicExecDeclare)s
+        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
 };
 }};
 
@@ -84,6 +89,9 @@ def template BranchImmCondConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -108,6 +116,9 @@ def template BranchRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -135,6 +146,9 @@ def template BranchRegCondConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -176,6 +190,9 @@ def template BranchRegRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -202,6 +219,26 @@ def template BranchImmRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
+
+def template BranchTarget {{
+
+    ArmISA::PCState
+    %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
+    {
+        %(op_decl)s;
+        %(op_rd)s;
+
+        ArmISA::PCState pcs = branchPC;
+        %(brTgtCode)s
+        pcs.advance();
+        return pcs;
+    }
+}};
+
+