diff options
author | Gabe Black <gabeblack@google.com> | 2018-10-12 23:32:43 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-01-14 21:29:28 +0000 |
commit | d4116b03ade72c8f0e73098d8a3f8563188717ac (patch) | |
tree | 6717f15d1756e0a71d744363619c8c3327cd80cb /src/arch/arm/isa/templates | |
parent | fd834ffb5334689792c81970c8da26ce27182932 (diff) | |
download | gem5-d4116b03ade72c8f0e73098d8a3f8563188717ac.tar.xz |
arm: Stop using the FloatReg and FloatRegBits types.
This will let us make those types 64 bits to be in line with the other
architectures.
Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa/templates')
-rw-r--r-- | src/arch/arm/isa/templates/crypto.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/neon.isa | 10 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/neon64.isa | 18 |
3 files changed, 15 insertions, 15 deletions
diff --git a/src/arch/arm/isa/templates/crypto.isa b/src/arch/arm/isa/templates/crypto.isa index 083ef1336..b432e9dfa 100644 --- a/src/arch/arm/isa/templates/crypto.isa +++ b/src/arch/arm/isa/templates/crypto.isa @@ -50,7 +50,7 @@ def template CryptoPredOpExecute {{ const unsigned rCount = %(r_count)d; union RegVect { - FloatRegBits regs[rCount]; + uint32_t regs[rCount]; }; if (%(predicate_test)s) diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index 35bd3865e..a3a6c1a94 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -216,10 +216,10 @@ def template NeonEqualRegExecute {{ %(op_rd)s; const unsigned rCount = %(r_count)d; - const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); + const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element); union RegVect { - FloatRegBits regs[rCount]; + uint32_t regs[rCount]; Element elements[eCount]; }; @@ -262,16 +262,16 @@ def template NeonUnequalRegExecute {{ %(op_rd)s; const unsigned rCount = %(r_count)d; - const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); + const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element); union RegVect { - FloatRegBits regs[rCount]; + uint32_t regs[rCount]; Element elements[eCount]; BigElement bigElements[eCount / 2]; }; union BigRegVect { - FloatRegBits regs[2 * rCount]; + uint32_t regs[2 * rCount]; BigElement elements[eCount]; }; diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa index 26e6d98b5..3c36e6bae 100644 --- a/src/arch/arm/isa/templates/neon64.isa +++ b/src/arch/arm/isa/templates/neon64.isa @@ -180,16 +180,16 @@ def template NeonXEqualRegOpExecute {{ %(op_rd)s; const unsigned rCount = %(r_count)d; - const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); - const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element); + const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element); + const unsigned eCountFull = 4 * sizeof(uint32_t) / sizeof(Element); union RegVect { - FloatRegBits regs[rCount]; + uint32_t regs[rCount]; Element elements[eCount]; }; union FullRegVect { - FloatRegBits regs[4]; + uint32_t regs[4]; Element elements[eCountFull]; }; @@ -214,22 +214,22 @@ def template NeonXUnequalRegOpExecute {{ %(op_rd)s; const unsigned rCount = %(r_count)d; - const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); - const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element); + const unsigned eCount = rCount * sizeof(uint32_t) / sizeof(Element); + const unsigned eCountFull = 4 * sizeof(uint32_t) / sizeof(Element); union RegVect { - FloatRegBits regs[rCount]; + uint32_t regs[rCount]; Element elements[eCount]; BigElement bigElements[eCount / 2]; }; union BigRegVect { - FloatRegBits regs[2 * rCount]; + uint32_t regs[2 * rCount]; BigElement elements[eCount]; }; union FullRegVect { - FloatRegBits regs[4]; + uint32_t regs[4]; Element elements[eCountFull]; }; |