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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:05 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:05 -0500
commit57443a2144c6f446c7b7a3de7389ae794d591330 (patch)
tree629d702a22392fd0651885f32bb1b53697b6fa54 /src/arch/arm/isa
parent1344fc2668eb4ea052a96d961e91d7578c8cb054 (diff)
downloadgem5-57443a2144c6f446c7b7a3de7389ae794d591330.tar.xz
ARM: Make LDM that loads the PC perform an interworking branch.
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/insts/macromem.isa2
-rw-r--r--src/arch/arm/isa/operands.isa2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 474e4fab0..13eb70b39 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -53,7 +53,7 @@ let {{
let {{
microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
'MicroMemOp',
- {'memacc_code': 'Ra = Mem;',
+ {'memacc_code': 'IWRa = Mem;',
'ea_code': 'EA = Rb + (up ? imm : -imm);',
'predicate_test': predicateTest},
['IsMicroop'])
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index c507864b6..c845acc94 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -129,6 +129,8 @@ def operands {{
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
+ 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11,
+ maybePCRead, maybeIWPCWrite),
'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11),
'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),