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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | cb9936cfdefdebf2c0b950f93a62d504d356524d (patch) | |
| tree | 3280784b875ccd23475c3f08edc774b50ef1c97d /src/arch/arm/isa | |
| parent | f246be4cbc27b4173f6917b430a31b9a39cdb380 (diff) | |
| download | gem5-cb9936cfdefdebf2c0b950f93a62d504d356524d.tar.xz | |
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 34 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 6 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/str.isa | 13 |
3 files changed, 22 insertions, 31 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 1c00a3d6b..be0e63900 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -138,47 +138,25 @@ let {{ return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); case MISCREG_TLBIALLIS: - return new WarnUnimplemented( - isRead ? "mrc tlbiallis" : "mcr tlbiallis", machInst); case MISCREG_TLBIMVAIS: - return new WarnUnimplemented( - isRead ? "mrc tlbimvais" : "mcr tlbimvais", machInst); case MISCREG_TLBIASIDIS: - return new WarnUnimplemented( - isRead ? "mrc tlbiasidis" : "mcr tlbiasidis", machInst); case MISCREG_TLBIMVAAIS: - return new WarnUnimplemented( - isRead ? "mrc tlbimvaais" : "mcr tlbimvaais", machInst); case MISCREG_ITLBIALL: - return new WarnUnimplemented( - isRead ? "mrc itlbiall" : "mcr itlbiall", machInst); case MISCREG_ITLBIMVA: - return new WarnUnimplemented( - isRead ? "mrc itlbimva" : "mcr itlbimva", machInst); case MISCREG_ITLBIASID: - return new WarnUnimplemented( - isRead ? "mrc itlbiasid" : "mcr itlbiasid", machInst); case MISCREG_DTLBIALL: - return new WarnUnimplemented( - isRead ? "mrc dtlbiall" : "mcr dtlbiall", machInst); case MISCREG_DTLBIMVA: - return new WarnUnimplemented( - isRead ? "mrc dtlbimva" : "mcr dtlbimva", machInst); case MISCREG_DTLBIASID: - return new WarnUnimplemented( - isRead ? "mrc dtlbiasid" : "mcr dtlbiasid", machInst); case MISCREG_TLBIALL: - return new WarnUnimplemented( - isRead ? "mrc tlbiall" : "mcr tlbiall", machInst); case MISCREG_TLBIMVA: - return new WarnUnimplemented( - isRead ? "mrc tlbimva" : "mcr tlbimva", machInst); case MISCREG_TLBIASID: - return new WarnUnimplemented( - isRead ? "mrc tlbiasid" : "mcr tlbiasid", machInst); case MISCREG_TLBIMVAA: - return new WarnUnimplemented( - isRead ? "mrc tlbimvaa" : "mcr tlbimvaa", machInst); + if (isRead) { + return new Unknown(machInst); + } else { + return new Mcr15(machInst, (IntRegIndex)miscReg, rt); + } + default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 40d9147df..093ff7a60 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -93,6 +93,9 @@ let {{ eaCode += ";" memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] + if user: + memFlags.append("ArmISA::TLB::UserMode") + if prefetch: Name = "%s_%s" % (mnem.upper(), Name) memFlags.append("Request::PREFETCH") @@ -179,6 +182,9 @@ let {{ eaCode += ";" memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"] + if user: + memFlags.append("ArmISA::TLB::UserMode") + if prefetch: Name = "%s_%s" % (mnem.upper(), Name) memFlags.append("Request::PREFETCH") diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index c8d2679fc..d86000947 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -107,6 +107,9 @@ let {{ accCode += "Base = Base %s;\n" % offset memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] + if user: + memFlags.append("ArmISA::TLB::UserMode") + if strex: memFlags.append("Request::LLSC") Name = "%s_%s" % (mnem.upper(), Name) @@ -184,10 +187,14 @@ let {{ accCode += "Base = Base %s;\n" % offset base = buildMemBase("MemoryReg", post, writeback) - emitStore(name, Name, False, eaCode, accCode, "",\ - ["ArmISA::TLB::MustBeOne", \ + memFlags = ["ArmISA::TLB::MustBeOne", \ "ArmISA::TLB::AllowUnaligned", \ - "%d" % (size - 1)], [], base) + "%d" % (size - 1)] + if user: + memFlags.append("ArmISA::TLB::UserMode") + + emitStore(name, Name, False, eaCode, accCode, "",\ + memFlags, [], base) def buildDoubleImmStore(mnem, post, add, writeback, \ strex=False, vstr=False): |