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author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 00:07:35 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 00:07:35 -0800 |
commit | 4a454c4f47362bd6f842fe1919f959a672ab1bb4 (patch) | |
tree | 23475b3ae66ce71d8d115b97230b62c3e3b9ea0a /src/arch/arm/isa | |
parent | 18b21c1ecaf7858c592c56cf4c12ec8781f821ba (diff) | |
download | gem5-4a454c4f47362bd6f842fe1919f959a672ab1bb4.tar.xz |
ARM: Set up an intregs.hh for ARM.
Add constants for all the modes and registers, maps for aliasing, functions
that use the maps and range check, and use a named constant instead of a magic
number for the microcode register.
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r-- | src/arch/arm/isa/formats/macromem.isa | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index 355a67ea9..d978967ac 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -213,9 +213,9 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) break; } - // Add 0 to Rn and stick it in Raddr (register 17). + // Add 0 to Rn and stick it in ureg0. // This is equivalent to a move. - microOps[0] = new MicroAddiUop(machInst, 17, RN, 0); + microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0); unsigned j = 0; for (int i = 1; i < ones+1; i++) { @@ -225,9 +225,11 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) regs_to_handle &= ~(1<<j); if (loadop) - microOps[i] = new MicroLdrUop(machInst, j, 17, start_addr); + microOps[i] = new MicroLdrUop(machInst, j, + INTREG_UREG0, start_addr); else - microOps[i] = new MicroStrUop(machInst, j, 17, start_addr); + microOps[i] = new MicroStrUop(machInst, j, + INTREG_UREG0, start_addr); if (up) start_addr += 4; |