CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU.  These changes have only been tested with the ARM ISA.  Other
ISAs potentially require modification.

2 files changed, 7 insertions, 5 deletions

diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index f20908d4f..222ecc647 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -247,7 +247,7 @@ let {{
     m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
                            { "code": m5checkpoint_code,
                              "predicate_test": predicateTest },
-                             ["IsNonSpeculative"])
+                             ["IsNonSpeculative", "IsUnverifiable"])
     header_output += BasicDeclare.subst(m5checkpointIop)
     decoder_output += BasicConstructor.subst(m5checkpointIop)
     exec_output += PredOpExecute.subst(m5checkpointIop)
@@ -260,7 +260,7 @@ let {{
     m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
                            { "code": m5readfileCode,
                              "predicate_test": predicateTest },
-                             ["IsNonSpeculative"])
+                             ["IsNonSpeculative", "IsUnverifiable"])
     header_output += BasicDeclare.subst(m5readfileIop)
     decoder_output += BasicConstructor.subst(m5readfileIop)
     exec_output += PredOpExecute.subst(m5readfileIop)
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 870f037d0..45d5d8d32 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -525,7 +525,8 @@ let {{
             { "code" : wfeCode,
               "pred_fixup" : wfePredFixUpCode,
               "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+            ["IsNonSpeculative", "IsQuiesce",
+             "IsSerializeAfter", "IsUnverifiable"])
     header_output += BasicDeclare.subst(wfeIop)
     decoder_output += BasicConstructor.subst(wfeIop)
     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
@@ -542,7 +543,8 @@ let {{
     '''
     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
             { "code" : wfiCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+            ["IsNonSpeculative", "IsQuiesce",
+             "IsSerializeAfter", "IsUnverifiable"])
     header_output += BasicDeclare.subst(wfiIop)
     decoder_output += BasicConstructor.subst(wfiIop)
     exec_output += QuiescePredOpExecute.subst(wfiIop)
@@ -565,7 +567,7 @@ let {{
     '''
     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
             { "code" : sevCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsSquashAfter"])
+            ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
     header_output += BasicDeclare.subst(sevIop)
     decoder_output += BasicConstructor.subst(sevIop)
     exec_output += PredOpExecute.subst(sevIop)