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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
| commit | da2a4acc26ba264c3c4a12495776fd6a1c4fb133 (patch) | |
| tree | f142100388b9d1403492c97b0d323728ce18ef8a /src/arch/arm/isa | |
| parent | 241cc0c8402f1b9f2ec20d1cc152d96930959b2a (diff) | |
| parent | a7394ad6807bd5e85f680184bf308673ca00534a (diff) | |
| download | gem5-da2a4acc26ba264c3c4a12495776fd6a1c4fb133.tar.xz | |
Merge yet again with the main repository.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/insts/m5ops.isa | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index a157b414c..da2e10886 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -190,12 +190,15 @@ let {{ exec_output += PredOpExecute.subst(loadsymbolIop) initparamCode = ''' - Rt = PseudoInst::initParam(xc->tcBase()); + uint64_t ip_val = PseudoInst::initParam(xc->tcBase()); + R0 = bits(ip_val, 31, 0); + R1 = bits(ip_val, 63, 32); ''' initparamIop = InstObjParams("initparam", "Initparam", "PredOp", { "code": initparamCode, - "predicate_test": predicateTest }) + "predicate_test": predicateTest }, + ["IsNonSpeculative"]) header_output += BasicDeclare.subst(initparamIop) decoder_output += BasicConstructor.subst(initparamIop) exec_output += PredOpExecute.subst(initparamIop) |