ARM: Ignore/warn on accesses to the dccmvac register.

1 files changed, 4 insertions, 1 deletions

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 2052e0d3d..8ba46960a 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -100,7 +100,10 @@ def format McrMrc15() {{
                     isRead ? "mrc dccisw" : "mcr dcisw", machInst);
           case MISCREG_DCCIMVAC:
             return new WarnUnimplemented(
-                    isRead ? "mrc dccimvac" : "mcr dcimvac", machInst);
+                    isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
+          case MISCREG_DCCMVAC:
+            return new WarnUnimplemented(
+                    isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
           case MISCREG_CP15ISB:
             return new WarnUnimplemented(
                     isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);