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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:07 -0500 |
| commit | c643b1c2749703b7823d665a7d89d0333f5c6e95 (patch) | |
| tree | cb9f0c6bbe54fae00f0803830bc9b2a04eea2bf3 /src/arch/arm/isa | |
| parent | 64ade8316ee563448d8c8f98a70cc4d9d0c66707 (diff) | |
| download | gem5-c643b1c2749703b7823d665a7d89d0333f5c6e95.tar.xz | |
ARM: Add a base class to support usada8.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index c845acc94..e2b73e2e2 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -102,6 +102,8 @@ def operands {{ maybePCRead, maybePCWrite), 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4, + maybePCRead, maybePCWrite), 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, maybePCRead, maybePCWrite), 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 8e781b540..7a9a35ec9 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -146,6 +146,32 @@ def template RegRegRegImmOpConstructor {{ } }}; +def template RegRegRegRegOpDeclare {{ +class %(class_name)s : public %(base_class)s +{ + protected: + public: + // Constructor + %(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, IntRegIndex _op1, + IntRegIndex _op2, IntRegIndex _op3); + %(BasicExecDeclare)s +}; +}}; + +def template RegRegRegRegOpConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, + IntRegIndex _op1, + IntRegIndex _op2, + IntRegIndex _op3) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _dest, _op1, _op2, _op3) + { + %(constructor)s; + } +}}; + def template RegRegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { |