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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-29 22:24:00 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-29 22:24:00 -0700 |
| commit | 4971331b4f8f9e79cf6dcc564a85fb432bef8b9c (patch) | |
| tree | eaa042986db612b3df7171b8e7430abd94a793ff /src/arch/arm/isa | |
| parent | e09ae149af4e97392a3ae7f8633c1bd18fe64e2d (diff) | |
| download | gem5-4971331b4f8f9e79cf6dcc564a85fb432bef8b9c.tar.xz | |
ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/pred.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index 50e162f3d..e90788c91 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -105,7 +105,8 @@ let {{ def getCcCode(flagtype): icReg = icImm = iv = '' if flagtype == "none": - icReg = icImm = iv = '1' + icReg = icImm = 'Cpsr<29:>' + iv = 'Cpsr<28:>' elif flagtype == "add": icReg = icImm = 'findCarry(32, resTemp, Rn, op2)' iv = 'findOverflow(32, resTemp, Rn, op2)' @@ -125,7 +126,8 @@ let {{ def getImmCcCode(flagtype): ivValue = icValue = '' if flagtype == "none": - icValue = ivValue = '1' + icValue = 'Cpsr<29:>' + ivValue = 'Cpsr<28:>' elif flagtype == "add": icValue = 'findCarry(32, resTemp, Rn, rotated_imm)' ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)' |