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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-14 19:22:30 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-14 19:22:30 -0800 |
| commit | c4042985d7b13ddd6afdd3748e9c619863f1233a (patch) | |
| tree | 6a3b641dbe2c4e789f8d826ded12bb3a051f42f7 /src/arch/arm/isa | |
| parent | e2ab64543b2a206c95fbf38565a50f0d5bba0f2a (diff) | |
| download | gem5-c4042985d7b13ddd6afdd3748e9c619863f1233a.tar.xz | |
ARM: Fix up the implmentation of the msr instruction.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/decoder.isa | 37 |
1 files changed, 27 insertions, 10 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index cd13fa420..5e82feb1b 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -113,17 +113,34 @@ format DataOp { 0x8: PredOp::mrs_cpsr({{ Rd = (Cpsr | CondCodes) & 0xF8FF03DF; }}); - 0x9: PredOp::msr_cpsr({{ - //assert(!RN<1:0>); - if (OPCODE_18) { - Cpsr = Cpsr<31:20> | mbits(Rm, 19, 16) | Cpsr<15:0>; - } - if (OPCODE_19) { - CondCodes = mbits(Rm, 31,27); - } - }}); + 0x9: decode USEIMM { + // The mask field is the same as the RN index. + 0: PredImmOp::msr_cpsr_imm({{ + uint32_t newCpsr = + cpsrWriteByInstr(Cpsr | CondCodes, + rotated_imm, RN, false); + Cpsr = ~CondCodesMask & newCpsr; + CondCodes = CondCodesMask & newCpsr; + }}); + 1: PredOp::msr_cpsr_reg({{ + uint32_t newCpsr = + cpsrWriteByInstr(Cpsr | CondCodes, + Rm, RN, false); + Cpsr = ~CondCodesMask & newCpsr; + CondCodes = CondCodesMask & newCpsr; + }}); + } 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); - 0xb: WarnUnimpl::msr_spsr(); + 0xb: decode USEIMM { + // The mask field is the same as the RN index. + 0: PredImmOp::msr_spsr_imm({{ + Spsr = spsrWriteByInstr(Spsr, rotated_imm, + RN, false); + }}); + 1: PredOp::msr_spsr_reg({{ + Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); + }}); + } } 0x1: decode OPCODE { 0x9: BranchExchange::bx({{ }}); |