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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | 1f032ad3452c2514287c142fb3faf953a5682ea3 (patch) | |
| tree | c37398638ecd1fcc43cb22c9c87f0384d7928127 /src/arch/arm/isa | |
| parent | 66bcbec96e9bb9619b306a281cb18e2b4cea91c5 (diff) | |
| download | gem5-1f032ad3452c2514287c142fb3faf953a5682ea3.tar.xz | |
ARM: Implement CLREX
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/uncond.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 11 |
3 files changed, 13 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index f203d5257..44a2f5251 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -194,7 +194,7 @@ def format Thumb32BranchesAndMiscCtrl() {{ case 0x1: return new Enterx(machInst); case 0x2: - return new WarnUnimplemented("clrex", machInst); + return new Clrex(machInst); case 0x4: return new WarnUnimplemented("dsb", machInst); case 0x5: diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index 079b472f3..92e4db22d 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -97,7 +97,7 @@ def format ArmUnconditional() {{ } else if (op1 == 0x57) { switch (op2) { case 0x1: - return new WarnUnimplemented("clrex", machInst); + return new Clrex(machInst); case 0x4: return new WarnUnimplemented("dsb", machInst); case 0x5: diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 341f3d1ce..09364cd23 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -668,6 +668,17 @@ let {{ decoder_output += ImmOpConstructor.subst(setendIop) exec_output += PredOpExecute.subst(setendIop) + clrexCode = ''' + unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC; + fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); + ''' + clrexIop = InstObjParams("clrex", "Clrex","PredOp", + { "code": clrexCode, + "predicate_test": predicateTest },[]) + header_output += BasicDeclare.subst(clrexIop) + decoder_output += BasicConstructor.subst(clrexIop) + exec_output += PredOpExecute.subst(clrexIop) + cpsCode = ''' uint32_t mode = bits(imm, 4, 0); uint32_t f = bits(imm, 5); |