merge mips fix and statetrace changes

3 files changed, 33 insertions, 7 deletions

diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 76d584858..a999b52e9 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -113,8 +113,7 @@ format DataOp {
                 0x1: decode OPCODE {
                     0x9: BranchExchange::bx({{ }});
                     0xb: PredOp::clz({{
-                        unsigned lsb = findLsbSet(Rm);
-                        Rd = (lsb > 31) ? 32 : lsb;
+                        Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
                     }});
                 }
                 0x2: decode OPCODE {
@@ -319,6 +318,10 @@ format DataOp {
             0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
             0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
         }
+        0xb: decode LOADOP {
+            0x0: WarnUnimpl::fstmx();
+            0x1: WarnUnimpl::fldmx();
+        }
     }
     0x7: decode OPCODE_24 {
         0: decode CPNUM {
@@ -417,12 +420,29 @@ format DataOp {
                     }
                 }
             }
+            0xa: decode MISC_OPCODE {
+                0x1: decode MEDIA_OPCODE {
+                    0xf: decode RN {
+                        0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
+                        0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
+                        0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
+                    }
+                    0xe: decode RN {
+                        0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
+                        0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
+                        0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
+                    }
+                }
+            }
         }
         format PredOp {
             // ARM System Call (SoftWare Interrupt)
             1: swi({{ if (testPredicate(Cpsr, condCode))
                       {
-                          xc->syscall(IMMED_23_0);
+                          if (IMMED_23_0)
+                              xc->syscall(IMMED_23_0);
+                          else
+                              xc->syscall(R7);
                       }
             }});
         }
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 50e162f3d..e90788c91 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -105,7 +105,8 @@ let {{
     def getCcCode(flagtype):
         icReg = icImm = iv = ''
         if flagtype == "none":
-            icReg = icImm = iv = '1'
+            icReg = icImm = 'Cpsr<29:>'
+            iv = 'Cpsr<28:>'
         elif flagtype == "add":
             icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
             iv = 'findOverflow(32, resTemp, Rn, op2)'
@@ -125,7 +126,8 @@ let {{
     def getImmCcCode(flagtype):
         ivValue = icValue = ''
         if flagtype == "none":
-            icValue = ivValue = '1'
+            icValue = 'Cpsr<29:>'
+            ivValue = 'Cpsr<28:>'
         elif flagtype == "add":
             icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
             ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index fa41918c1..ac7427dad 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -57,6 +57,7 @@ def operands {{
     'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
+    'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
 
     #Destination register for load/store double instructions
     'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
@@ -81,7 +82,10 @@ def operands {{
 
     'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
     'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
-    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
-    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
+    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
+    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
+    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
+    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
+    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
 
 }};