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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
| commit | b5cfa9361b26eda818cd5810d5f4e8ae3fce5d0d (patch) | |
| tree | 827166559072c9f3f1546d15d78690af03ebb06d /src/arch/arm/isa | |
| parent | 556ea0ee571a20352856217427ec42e337ea4734 (diff) | |
| download | gem5-b5cfa9361b26eda818cd5810d5f4e8ae3fce5d0d.tar.xz | |
ARM: Convert the CP15 registers from MPU to MMU.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index d01b5014d..8d386b0b0 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -128,15 +128,6 @@ def format McrMrc15() {{ case MISCREG_BPIALL: return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); - case MISCREG_DRBAR: - return new WarnUnimplemented( - isRead ? "mrc drbar" : "mcr drbar", machInst); - case MISCREG_DRACR: - return new WarnUnimplemented( - isRead ? "mrc dracr" : "mcr dracr", machInst); - case MISCREG_DRSR: - return new WarnUnimplemented( - isRead ? "mrc drsr" : "mcr drsr", machInst); default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); |