Automated merge with ssh://hg@repo.m5sim.org/m5

13 files changed, 266 insertions, 79 deletions

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 3a0cad1c5..2267ee34f 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -143,7 +143,7 @@ let {{
                                                  bits(machInst, 22) << 4);
         const uint32_t type = bits(machInst, 11, 8);
         uint32_t size = 0;
-        uint32_t align = 0;
+        uint32_t align = TLB::MustBeOne;
         unsigned inc = 1;
         unsigned regs = 1;
         unsigned lane = 0;
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index d8ea2118e..84b9bb720 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -48,6 +48,8 @@ let {{
         bCode = '''
         NPC = (uint32_t)(PC + imm);
         '''
+        br_tgt_code = '''pcs.instNPC(branchPC.instPC() + imm);'''
+        instFlags = ["IsDirectControl"]
         if (link):
             bCode += '''
                 if (Thumb)
@@ -55,12 +57,15 @@ let {{
                 else
                     LR = PC - 4;
             '''
+            instFlags += ["IsCall"]
+
 
         bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
-                             {"code": bCode,
-                              "predicate_test": predicateTest})
+                             {"code": bCode, "predicate_test": predicateTest,
+                             "brTgtCode" : br_tgt_code}, instFlags)
         header_output += BranchImmCondDeclare.subst(bIop)
-        decoder_output += BranchImmCondConstructor.subst(bIop)
+        decoder_output += BranchImmCondConstructor.subst(bIop) + \
+                       BranchTarget.subst(bIop)
         exec_output += PredOpExecute.subst(bIop)
 
     # BX, BLX
@@ -81,15 +86,22 @@ let {{
             # Since we're switching ISAs, the target ISA will be the opposite
             # of the current ISA. Thumb is whether the target is ARM.
             newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
+            br_tgt_code = '''
+            pcs.instNPC((branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
+                                (branchPC.instPC() + imm)));
+            '''
             base = "BranchImmCond"
             declare = BranchImmCondDeclare
             constructor = BranchImmCondConstructor
+            instFlags = ["IsDirectControl"]
         else:
             Name += "Reg"
             newPC = 'Op1'
+            br_tgt_code = ''
             base = "BranchRegCond"
             declare = BranchRegCondDeclare
             constructor = BranchRegCondConstructor
+            instFlags = ["IsIndirectControl"]
         if link and imm:
             linkStr = '''
                 // The immediate version of the blx thumb instruction
@@ -100,6 +112,7 @@ let {{
                 else
                     LR = PC - 4;
             '''
+            instFlags += ["IsCall"]
         elif link:
             linkStr = '''
                 if (Thumb)
@@ -107,14 +120,18 @@ let {{
                 else
                     LR = PC - 4;
             '''
+            instFlags += ["IsCall"]
         else:
             linkStr = ""
+            instFlags += ["IsReturn"]
 
         if imm and link: #blx with imm
             branchStr = '''
                 NextThumb = !Thumb;
                 NPC = %(newPC)s;
             '''
+            br_tgt_code = '''pcs.nextThumb(!branchPC.thumb());\n''' + \
+                          br_tgt_code
         else:
             branchStr = "IWNPC = %(newPC)s;"
         branchStr = branchStr % { "newPC" : newPC }
@@ -123,11 +140,13 @@ let {{
                           "newPC": newPC,
                           "branch": branchStr}
         blxIop = InstObjParams(mnem, Name, base,
-                               {"code": code,
-                                "predicate_test": predicateTest})
+                               {"code": code, "brTgtCode" : br_tgt_code,
+                                "predicate_test": predicateTest}, instFlags)
         header_output += declare.subst(blxIop)
         decoder_output += constructor.subst(blxIop)
         exec_output += PredOpExecute.subst(blxIop)
+        if imm:
+            decoder_output += BranchTarget.subst(blxIop)
 
     #Ignore BXJ for now
 
@@ -136,7 +155,8 @@ let {{
         code = 'NPC = (uint32_t)(PC + imm);\n'
         predTest = "Op1 %(test)s 0" % {"test": test}
         iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
-                            {"code": code, "predicate_test": predTest})
+                            {"code": code, "predicate_test": predTest},
+                            ["IsIndirectControl"])
         header_output += BranchImmRegDeclare.subst(iop)
         decoder_output += BranchImmRegConstructor.subst(iop)
         exec_output += PredOpExecute.subst(iop)
@@ -164,7 +184,8 @@ let {{
         iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
                             {'ea_code': eaCode,
                              'memacc_code': accCode,
-                             'predicate_test': predicateTest})
+                             'predicate_test': predicateTest},
+                             ["IsIndirectControl"])
         header_output += BranchTableDeclare.subst(iop)
         decoder_output += BranchRegRegConstructor.subst(iop)
         exec_output += LoadExecute.subst(iop) + \
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index c60a91a50..2e45f2875 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -67,7 +67,7 @@ let {{
             self.memFlags = ["ArmISA::TLB::MustBeOne"]
             self.codeBlobs = {"postacc_code" : ""}
 
-        def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
+        def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None):
 
             global header_output, decoder_output, exec_output
 
@@ -76,7 +76,8 @@ let {{
             (newHeader,
              newDecoder,
              newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
-                                           self.memFlags, instFlags, base, wbDecl)
+                                           self.memFlags, instFlags, base,
+                                           wbDecl, pcDecl)
 
             header_output += newHeader
             decoder_output += newDecoder
@@ -104,26 +105,18 @@ let {{
                 wbDiff = 8
             accCode = '''
             CPSR cpsr = Cpsr;
-            SCTLR sctlr = Sctlr;
-            // Use the version of NPC that gets set before NextThumb
-            pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
-            uint32_t tempSpsr = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
-            uint32_t newCpsr =
-                cpsrWriteByInstr(cpsr | CondCodes, tempSpsr,
-                                 0xF, true, sctlr.nmfi);
-            Cpsr = ~CondCodesMask & newCpsr;
-            NextThumb = ((CPSR)newCpsr).t;
-            NextJazelle = ((CPSR)newCpsr).j;
-            ForcedItState = ((((CPSR)tempSpsr).it2 << 2) & 0xFC)
-                | (((CPSR)tempSpsr).it1 & 0x3);
-            CondCodes = CondCodesMask & newCpsr;
+            URc = cpsr | CondCodes;
+            URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
+            URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
             '''
             self.codeBlobs["memacc_code"] = accCode
 
             wbDecl = None
+            pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);"
+
             if self.writeback:
                 wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
-            self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"])
+            self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"], pcDecl)
 
     class LoadImmInst(LoadInst):
         def __init__(self, *args, **kargs):
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index da3609bbc..8521cbc97 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -66,7 +66,7 @@ let {{
                              ["IsNonSpeculative", "IsQuiesce"])
     header_output += BasicDeclare.subst(quiesceIop)
     decoder_output += BasicConstructor.subst(quiesceIop)
-    exec_output += PredOpExecute.subst(quiesceIop)
+    exec_output += QuiescePredOpExecute.subst(quiesceIop)
 
     quiesceNsCode = '''
 #if FULL_SYSTEM
@@ -80,7 +80,7 @@ let {{
                              ["IsNonSpeculative", "IsQuiesce"])
     header_output += BasicDeclare.subst(quiesceNsIop)
     decoder_output += BasicConstructor.subst(quiesceNsIop)
-    exec_output += PredOpExecute.subst(quiesceNsIop)
+    exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
 
     quiesceCyclesCode = '''
 #if FULL_SYSTEM
@@ -94,7 +94,7 @@ let {{
                              ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
     header_output += BasicDeclare.subst(quiesceCyclesIop)
     decoder_output += BasicConstructor.subst(quiesceCyclesIop)
-    exec_output += PredOpExecute.subst(quiesceCyclesIop)
+    exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
 
     quiesceTimeCode = '''
 #if FULL_SYSTEM
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 33d57a60b..15879e0e3 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -51,7 +51,7 @@ let {{
     microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
                                    'MicroMemOp',
                                    {'memacc_code': microLdrUopCode,
-                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
+                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
@@ -60,7 +60,7 @@ let {{
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
                                        'ea_code': vfpEnabledCheckCode +
-                                           'EA = Rb + (up ? imm : -imm);',
+                                           'EA = URb + (up ? imm : -imm);',
                                        'predicate_test': predicateTest},
                                       ['IsMicroop'])
 
@@ -69,7 +69,7 @@ let {{
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
                                        'ea_code': vfpEnabledCheckCode + '''
-                                        EA = Rb + (up ? imm : -imm) +
+                                        EA = URb + (up ? imm : -imm) +
                                              (((CPSR)Cpsr).e ? 4 : 0);
                                         ''',
                                        'predicate_test': predicateTest},
@@ -80,37 +80,40 @@ let {{
                                       'MicroMemOp',
                                       {'memacc_code': microLdrFpUopCode,
                                        'ea_code': vfpEnabledCheckCode + '''
-                                        EA = Rb + (up ? imm : -imm) -
+                                        EA = URb + (up ? imm : -imm) -
                                              (((CPSR)Cpsr).e ? 4 : 0);
                                         ''',
                                        'predicate_test': predicateTest},
                                       ['IsMicroop'])
 
-    microLdrRetUopCode = '''
+    microRetUopCode = '''
         CPSR cpsr = Cpsr;
         SCTLR sctlr = Sctlr;
         uint32_t newCpsr =
             cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
-        IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
+        IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
         ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
                 | (((CPSR)Spsr).it1 & 0x3);
     '''
+
     microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
                                       'MicroMemOp',
-                                      {'memacc_code': microLdrRetUopCode,
+                                      {'memacc_code':
+                                          microRetUopCode % 'Mem.uw',
                                        'ea_code':
-                                          'EA = Rb + (up ? imm : -imm);',
+                                          'EA = URb + (up ? imm : -imm);',
                                        'predicate_test': condPredicateTest},
-                                      ['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
+                                      ['IsMicroop','IsNonSpeculative',
+                                       'IsSerializeAfter'])
 
-    microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
+    microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
     microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
                                    'MicroMemOp',
                                    {'memacc_code': microStrUopCode,
                                     'postacc_code': "",
-                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
+                                    'ea_code': 'EA = URb + (up ? imm : -imm);',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
@@ -120,7 +123,7 @@ let {{
                                      {'memacc_code': microStrFpUopCode,
                                       'postacc_code': "",
                                       'ea_code': vfpEnabledCheckCode +
-                                           'EA = Rb + (up ? imm : -imm);',
+                                           'EA = URb + (up ? imm : -imm);',
                                       'predicate_test': predicateTest},
                                      ['IsMicroop'])
 
@@ -130,7 +133,7 @@ let {{
                                        {'memacc_code': microStrFpUopCode,
                                         'postacc_code': "",
                                         'ea_code': vfpEnabledCheckCode + '''
-                                         EA = Rb + (up ? imm : -imm) +
+                                         EA = URb + (up ? imm : -imm) +
                                               (((CPSR)Cpsr).e ? 4 : 0);
                                          ''',
                                         'predicate_test': predicateTest},
@@ -142,7 +145,7 @@ let {{
                                        {'memacc_code': microStrFpUopCode,
                                         'postacc_code': "",
                                         'ea_code': vfpEnabledCheckCode + '''
-                                         EA = Rb + (up ? imm : -imm) -
+                                         EA = URb + (up ? imm : -imm) -
                                               (((CPSR)Cpsr).e ? 4 : 0);
                                          ''',
                                         'predicate_test': predicateTest},
@@ -170,7 +173,7 @@ let {{
 let {{
     exec_output = header_output = ''
 
-    eaCode = 'EA = Ra + imm;'
+    eaCode = 'EA = URa + imm;'
 
     for size in (1, 2, 3, 4, 6, 8, 12, 16):
         # Set up the memory access.
@@ -572,14 +575,14 @@ let {{
 let {{
     microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
                                     'MicroIntImmOp',
-                                    {'code': 'Ra = Rb + imm;',
+                                    {'code': 'URa = URb + imm;',
                                      'predicate_test': predicateTest},
                                     ['IsMicroop'])
 
     microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
                                    'MicroIntRegOp',
                                    {'code':
-                                    '''Ra = Rb + shift_rm_imm(Rc, shiftAmt,
+                                    '''URa = URb + shift_rm_imm(URc, shiftAmt,
                                                               shiftType,
                                                               CondCodes<29:>);
                                     ''',
@@ -588,14 +591,14 @@ let {{
 
     microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
                                     'MicroIntImmOp',
-                                    {'code': 'Ra = Rb - imm;',
+                                    {'code': 'URa = URb - imm;',
                                      'predicate_test': predicateTest},
                                     ['IsMicroop'])
 
     microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
                                    'MicroIntRegOp',
                                    {'code':
-                                    '''Ra = Rb - shift_rm_imm(Rc, shiftAmt,
+                                    '''URa = URb - shift_rm_imm(URc, shiftAmt,
                                                               shiftType,
                                                               CondCodes<29:>);
                                     ''',
@@ -604,27 +607,62 @@ let {{
 
     microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
                                    'MicroIntMov',
-                                   {'code': 'IWRa = Rb;',
+                                   {'code': 'IWRa = URb;',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])
 
+    microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
+                                      'MicroIntMov',
+                                     {'code': microRetUopCode % 'URb',
+                                      'predicate_test': predicateTest},
+                                     ['IsMicroop', 'IsNonSpeculative',
+                                      'IsSerializeAfter'])
+
+    setPCCPSRDecl = '''
+                    CPSR cpsrOrCondCodes = URc;
+                    SCTLR sctlr = Sctlr;
+                    pNPC = URa;
+                    uint32_t newCpsr =
+                    cpsrWriteByInstr(cpsrOrCondCodes, URb,
+                                     0xF, true, sctlr.nmfi);
+                    Cpsr = ~CondCodesMask & newCpsr;
+                    NextThumb = ((CPSR)newCpsr).t;
+                    NextJazelle = ((CPSR)newCpsr).j;
+                    ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC)
+                                    | (((CPSR)URb).it1 & 0x3);
+                    CondCodes = CondCodesMask & newCpsr;
+                    '''
+
+    microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
+                                         'MicroSetPCCPSR',
+                                         {'code': setPCCPSRDecl,
+                                          'predicate_test': predicateTest},
+                                         ['IsMicroop'])
+
     header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
                     MicroIntImmDeclare.subst(microSubiUopIop) + \
                     MicroIntRegDeclare.subst(microAddUopIop) + \
                     MicroIntRegDeclare.subst(microSubUopIop) + \
-                    MicroIntMovDeclare.subst(microUopRegMovIop)
+                    MicroIntMovDeclare.subst(microUopRegMovIop) + \
+                    MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
+                    MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
 
     decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
                      MicroIntImmConstructor.subst(microSubiUopIop) + \
                      MicroIntRegConstructor.subst(microAddUopIop) + \
                      MicroIntRegConstructor.subst(microSubUopIop) + \
-                     MicroIntMovConstructor.subst(microUopRegMovIop)
+                     MicroIntMovConstructor.subst(microUopRegMovIop) + \
+                     MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
+                     MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
 
     exec_output = PredOpExecute.subst(microAddiUopIop) + \
                   PredOpExecute.subst(microSubiUopIop) + \
                   PredOpExecute.subst(microAddUopIop) + \
                   PredOpExecute.subst(microSubUopIop) + \
-                  PredOpExecute.subst(microUopRegMovIop)
+                  PredOpExecute.subst(microUopRegMovIop) + \
+                  PredOpExecute.subst(microUopRegMovRetIop) + \
+                  PredOpExecute.subst(microUopSetPCCPSRIop)
+
 }};
 
 let {{
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index 507f8cd4b..d0c0f0710 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -48,7 +48,7 @@ let {{
             self.constructTemplate = eval(self.decConstBase + 'Constructor')
 
         def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
-                          base = 'Memory', wbDecl = None):
+                          base = 'Memory', wbDecl = None, pcDecl = None):
             # Make sure flags are in lists (convert to lists if not).
             memFlags = makeList(memFlags)
             instFlags = makeList(instFlags)
@@ -65,12 +65,26 @@ let {{
             macroName = Name
             instFlagsCopy = list(instFlags)
             codeBlobsCopy = dict(codeBlobs)
-            if wbDecl is not None:
+
+            use_uops = 0
+            if wbDecl is not None or pcDecl is not None:
                 instFlagsCopy.append('IsMicroop')
                 Name = Name + 'Acc'
+                use_uops = 1
+
+            use_wb = 0
+            use_pc = 0
+            if wbDecl is not None:
+                use_wb = 1
+            if pcDecl is not None:
+                use_pc = 1
+
             codeBlobsCopy['acc_name'] = Name
             codeBlobsCopy['wb_decl'] = wbDecl
+            codeBlobsCopy['pc_decl'] = pcDecl
             codeBlobsCopy['use_uops'] = 0
+            codeBlobsCopy['use_wb'] = 0
+            codeBlobsCopy['use_pc'] = 0
 
             iop = InstObjParams(name, Name, base,
                                 codeBlobsCopy, instFlagsCopy)
@@ -81,11 +95,14 @@ let {{
                           self.initiateAccTemplate.subst(iop) + \
                           self.completeAccTemplate.subst(iop)
 
-            if wbDecl is not None:
+            if wbDecl is not None or pcDecl is not None:
                 iop = InstObjParams(name, macroName, base,
                                     { "wb_decl" : wbDecl,
+                                      "pc_decl" : pcDecl,
                                       "acc_name" : Name,
-                                      "use_uops" : 1 },
+                                      "use_uops" : use_uops,
+                                      "use_pc" : use_pc,
+                                      "use_wb" : use_wb },
                                     ['IsMacroop'])
                 header_output += self.declareTemplate.subst(iop)
                 decoder_output += self.constructTemplate.subst(iop)
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index be51d927d..cf5c7b47a 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -491,10 +491,13 @@ let {{
 
     wfeCode = '''
 #if FULL_SYSTEM
-    if (SevMailbox)
+    if (SevMailbox) {
         SevMailbox = 0;
-    else
+        PseudoInst::quiesceSkip(xc->tcBase());
+    }
+    else {
         PseudoInst::quiesce(xc->tcBase());
+    }
 #endif
     '''
     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
@@ -502,7 +505,7 @@ let {{
             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
     header_output += BasicDeclare.subst(wfeIop)
     decoder_output += BasicConstructor.subst(wfeIop)
-    exec_output += PredOpExecute.subst(wfeIop)
+    exec_output += QuiescePredOpExecute.subst(wfeIop)
 
     wfiCode = '''
 #if FULL_SYSTEM
@@ -511,22 +514,25 @@ let {{
     '''
     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
             { "code" : wfiCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce"])
+            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
     header_output += BasicDeclare.subst(wfiIop)
     decoder_output += BasicConstructor.subst(wfiIop)
-    exec_output += PredOpExecute.subst(wfiIop)
+    exec_output += QuiescePredOpExecute.subst(wfiIop)
 
     sevCode = '''
     // Need a way for O3 to not scoreboard these accesses as pipe flushes.
+    SevMailbox = 1;
     System *sys = xc->tcBase()->getSystemPtr();
     for (int x = 0; x < sys->numContexts(); x++) {
         ThreadContext *oc = sys->getThreadContext(x);
-        oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+        if (oc != xc->tcBase()) {
+            oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+        }
     }
     '''
     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
             { "code" : sevCode, "predicate_test" : predicateTest },
-            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+            ["IsNonSpeculative", "IsSquashAfter"])
     header_output += BasicDeclare.subst(sevIop)
     decoder_output += BasicConstructor.subst(sevIop)
     exec_output += PredOpExecute.subst(sevIop)
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index f661961f7..e5d47c28f 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -222,7 +222,6 @@ let {{
         decConstBase = 'StoreExImm'
         basePrefix = 'MemoryExImm'
         nameFunc = staticmethod(storeImmClassName)
-        instFlags = ['IsStoreConditional']
 
         def __init__(self, *args, **kargs):
             super(StoreImmEx, self).__init__(*args, **kargs)
@@ -302,7 +301,6 @@ let {{
         decConstBase = 'StoreExDImm'
         basePrefix = 'MemoryExDImm'
         nameFunc = staticmethod(storeDoubleImmClassName)
-        instFlags = ['IsStoreConditional']
 
         def __init__(self, *args, **kargs):
             super(StoreDoubleImmEx, self).__init__(*args, **kargs)
@@ -370,10 +368,14 @@ let {{
 
     buildDoubleStores("strd")
 
-    StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
-    StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
-    StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
-    StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
+    StoreImmEx("strex", False, True, False, size=4, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
+    StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
+    StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
+    StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive",
+               instFlags = ['IsStoreConditional']).emit()
 
     StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
     StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index f403f9372..7b014acd0 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -228,11 +228,11 @@ def operands {{
     'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
 
     #Register fields for microops
-    'Ra' : intReg('ura'),
+    'URa' : intReg('ura'),
     'IWRa' : intRegIWPC('ura'),
     'Fa' : floatReg('ura'),
-    'Rb' : intReg('urb'),
-    'Rc' : intReg('urc'),
+    'URb' : intReg('urb'),
+    'URc' : intReg('urc'),
 
     #Memory Operand
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index d1f581f51..6abf76963 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -57,7 +57,11 @@ def template BranchImmConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
+
     }
 }};
 
@@ -69,6 +73,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, int32_t _imm,
                        ConditionCode _condCode);
         %(BasicExecDeclare)s
+        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
 };
 }};
 
@@ -84,6 +89,9 @@ def template BranchImmCondConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -108,6 +116,9 @@ def template BranchRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -135,6 +146,9 @@ def template BranchRegCondConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -176,6 +190,9 @@ def template BranchRegRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
@@ -202,6 +219,26 @@ def template BranchImmRegConstructor {{
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
+            flags[IsCondControl] = true;
+        } else {
+            flags[IsUncondControl] = true;
         }
     }
 }};
+
+def template BranchTarget {{
+
+    ArmISA::PCState
+    %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
+    {
+        %(op_decl)s;
+        %(op_rd)s;
+
+        ArmISA::PCState pcs = branchPC;
+        %(brTgtCode)s
+        pcs.advance();
+        return pcs;
+    }
+}};
+
+
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index b7ca7fa48..a7f7f0da8 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -109,6 +109,41 @@ def template MicroNeonMemDeclare {{
 
 ////////////////////////////////////////////////////////////////////
 //
+// PC   = Integer(ura)
+// CPSR = Integer(urb)
+//
+
+def template MicroSetPCCPSRDeclare {{
+    class %(class_name)s : public %(base_class)s
+    {
+      public:
+        %(class_name)s(ExtMachInst machInst,
+                       IntRegIndex _ura,
+                       IntRegIndex _urb,
+                       IntRegIndex _urc);
+        %(BasicExecDeclare)s
+    };
+}};
+
+def template MicroSetPCCPSRConstructor {{
+    %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                   IntRegIndex _ura,
+                                   IntRegIndex _urb,
+                                   IntRegIndex _urc)
+          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                           _ura, _urb, _urc)
+    {
+        %(constructor)s;
+        if (!(condCode == COND_AL || condCode == COND_UC)) {
+            for (int x = 0; x < _numDestRegs; x++) {
+                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            }
+        }
+    }
+}};
+
+////////////////////////////////////////////////////////////////////
+//
 // Integer = Integer op Integer microops
 //
 
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 3d073b322..dcfd47ace 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -917,9 +917,9 @@ def template CompleteAccDeclare {{
 
 def template RfeConstructor {{
     inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
-            uint32_t _base, int _mode, bool _wb)
-         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
-                 (IntRegIndex)_base, (AddrMode)_mode, _wb)
+                                          uint32_t _base, int _mode, bool _wb)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                         (IntRegIndex)_base, (AddrMode)_mode, _wb)
     {
         %(constructor)s;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
@@ -928,12 +928,18 @@ def template RfeConstructor {{
             }
         }
 #if %(use_uops)d
-        assert(numMicroops >= 2);
-        uops = new StaticInstPtr[numMicroops];
-        uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
-        uops[0]->setDelayedCommit();
-        uops[1] = new %(wb_decl)s;
-        uops[1]->setLastMicroop();
+        uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
+        int uopIdx = 0;
+        uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
+        uops[uopIdx]->setDelayedCommit();
+#if %(use_wb)d
+        uops[++uopIdx] = new %(wb_decl)s;
+        uops[uopIdx]->setDelayedCommit();
+#endif
+#if %(use_pc)d
+        uops[++uopIdx] = new %(pc_decl)s;
+#endif
+        uops[uopIdx]->setLastMicroop();
 #endif
     }
 }};
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index c9e7b1803..2a4bd9dab 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -170,6 +170,38 @@ def template PredOpExecute {{
     }
 }};
 
+def template QuiescePredOpExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+        uint64_t resTemp = 0;
+        resTemp = resTemp;
+        %(op_decl)s;
+        %(op_rd)s;
+
+        if (%(predicate_test)s)
+        {
+            %(code)s;
+            if (fault == NoFault)
+            {
+                %(op_wb)s;
+            }
+        } else {
+            xc->setPredicate(false);
+#if FULL_SYSTEM
+            PseudoInst::quiesceSkip(xc->tcBase());
+#endif
+        }
+
+        if (fault == NoFault && machInst.itstateMask != 0&&
+                (!isMicroop() || isLastMicroop())) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
+        return fault;
+    }
+}};
+
 def template DataDecode {{
     if (machInst.opcode4 == 0) {
         if (machInst.sField == 0)