ARM: Pull some static code out of the isa desc and create miscregs.hh.

6 files changed, 28 insertions, 100 deletions

diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 459c9788e..b84109546 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -830,7 +830,7 @@ decode COND_CODE default Unknown::unknown() {
             }
             format PredOp {
                 // ARM System Call (SoftWare Interrupt)
-                1: swi({{ if (arm_predicate(xc->readMiscReg(ArmISA::CPSR),
+                1: swi({{ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
                               condCode))
                           {
                               //xc->syscall(R7);
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 40aa4a952..15965d3e0 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -234,7 +234,7 @@ def format Branch(code,*opt_flags) {{
     else:
          inst_flags += ('IsCondControl', )
 
-    icode =  'if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode)) {\n'
+    icode =  'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n'
     icode += code
     icode += '  NPC = NPC + 4 + disp;\n'
     icode += '} else {\n'
@@ -268,7 +268,7 @@ def format BranchExchange(code,*opt_flags) {{
 
     #Condition code
 
-    icode =  'if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode)) {\n'
+    icode =  'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n'
     icode += code
     icode += '  NPC = Rm & 0xfffffffe; // Masks off bottom bit\n'
     icode += '} else {\n'
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 682c76079..1dd05c223 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -67,7 +67,7 @@ def template FPAExecute {{
 
                 %(code)s;
 
-                if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode) &&
+                if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode) &&
                         fault == NoFault)
                 {
                     %(op_wb)s;
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index df1d067dc..4da37c3e7 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -216,7 +216,7 @@ def template EACompExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 %(op_wb)s;
@@ -241,7 +241,7 @@ def template LoadMemAccExecute {{
         %(op_rd)s;
         EA = xc->getEA();
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
@@ -270,7 +270,7 @@ def template LoadExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
@@ -299,7 +299,7 @@ def template LoadInitiateAcc {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
@@ -322,7 +322,7 @@ def template LoadCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             // ARM instructions will not have a pkt if the predicate is false
             Mem = pkt->get<typeof(Mem)>();
@@ -353,7 +353,7 @@ def template StoreMemAccExecute {{
         %(op_decl)s;
         %(op_rd)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             EA = xc->getEA();
 
@@ -385,7 +385,7 @@ def template StoreExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 %(memacc_code)s;
@@ -418,7 +418,7 @@ def template StoreInitiateAcc {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 %(memacc_code)s;
@@ -451,7 +451,7 @@ def template StoreCompleteAcc {{
         %(fp_enable_check)s;
         %(op_dest_decl)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 %(op_wb)s;
@@ -472,7 +472,7 @@ def template StoreCondCompleteAcc {{
         %(fp_enable_check)s;
         %(op_dest_decl)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 %(op_wb)s;
@@ -495,7 +495,7 @@ def template MiscMemAccExecute {{
         %(op_decl)s;
         %(op_rd)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             EA = xc->getEA();
 
@@ -520,7 +520,7 @@ def template MiscExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault) {
                 %(memacc_code)s;
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 1e9dba07e..de9f4d316 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -36,25 +36,6 @@
 output header {{
 #include <iostream>
 
-    enum ArmPredicateBits {
-        COND_EQ  =   0,
-        COND_NE, //  1
-        COND_CS, //  2
-        COND_CC, //  3
-        COND_MI, //  4
-        COND_PL, //  5
-        COND_VS, //  6
-        COND_VC, //  7
-        COND_HI, //  8
-        COND_LS, //  9
-        COND_GE, // 10
-        COND_LT, // 11
-        COND_GT, // 12
-        COND_LE, // 13
-        COND_AL, // 14
-        COND_NV  // 15
-    };
-
     inline uint32_t
     rotate_imm(uint32_t immValue, uint32_t rotateValue)
     {
@@ -62,76 +43,23 @@ output header {{
                 (immValue << (32 - (int)(rotateValue & 31))));
     }
 
-    inline uint32_t nSet(uint32_t cpsr) { return cpsr & (1<<31); }
-    inline uint32_t zSet(uint32_t cpsr) { return cpsr & (1<<30); }
-    inline uint32_t cSet(uint32_t cpsr) { return cpsr & (1<<29); }
-    inline uint32_t vSet(uint32_t cpsr) { return cpsr & (1<<28); }
-
-    inline bool arm_predicate(uint32_t cpsr, uint32_t predBits)
-    {
-
-        enum ArmPredicateBits armPredBits = (enum ArmPredicateBits) predBits;
-        uint32_t result = 0;
-        switch (armPredBits)
-        {
-            case COND_EQ:
-                result = zSet(cpsr); break;
-            case COND_NE:
-                result = !zSet(cpsr); break;
-            case COND_CS:
-                result = cSet(cpsr); break;
-            case COND_CC:
-                result = !cSet(cpsr); break;
-            case COND_MI:
-                result = nSet(cpsr); break;
-            case COND_PL:
-                result = !nSet(cpsr); break;
-            case COND_VS:
-                result = vSet(cpsr); break;
-            case COND_VC:
-                result = !vSet(cpsr); break;
-            case COND_HI:
-                result = cSet(cpsr) && !zSet(cpsr); break;
-            case COND_LS:
-                result = !cSet(cpsr) || zSet(cpsr); break;
-            case COND_GE:
-                result = (!nSet(cpsr) && !vSet(cpsr)) || (nSet(cpsr) && vSet(cpsr)); break;
-            case COND_LT:
-                result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)); break;
-            case COND_GT:
-                result = (!nSet(cpsr) && !vSet(cpsr) && !zSet(cpsr)) || (nSet(cpsr) && vSet(cpsr) && !zSet(cpsr)); break;
-            case COND_LE:
-                result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)) || zSet(cpsr); break;
-            case COND_AL: result = 1; break;
-            case COND_NV: result = 0; break;
-            default:
-                fprintf(stderr, "Unhandled predicate condition: %d\n", armPredBits);
-                exit(1);
-        }
-        if (result)
-            return true;
-        else
-            return false;
-    }
-
-
     /**
      * Base class for predicated integer operations.
      */
     class PredOp : public ArmStaticInst
     {
-            protected:
+      protected:
 
-            uint32_t condCode;
+        ArmISA::ConditionCode condCode;
 
-            /// Constructor
-            PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                            ArmStaticInst(mnem, _machInst, __opClass),
-                            condCode(COND_CODE)
-            {
-            }
+        /// Constructor
+        PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                        ArmStaticInst(mnem, _machInst, __opClass),
+                        condCode((ArmISA::ConditionCode)COND_CODE)
+        {
+        }
 
-            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
     };
 
     /**
@@ -243,7 +171,7 @@ def template PredOpExecute {{
         %(op_rd)s;
         %(code)s;
 
-        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+        if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
         {
             if (fault == NoFault)
             {
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index b2c4f8420..f82e49109 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -64,8 +64,8 @@ def operands {{
     #Memory Operand
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
 
-    'Cpsr': ('ControlReg', 'uw', 'CPSR', 'IsInteger', 7),
-    'Fpsr': ('ControlReg', 'uw', 'FPSR', 'IsInteger', 7),
+    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
+    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
     'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
     'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),