diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2009-11-17 18:02:08 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2009-11-17 18:02:08 -0600 |
commit | 0916c376a97dacf5d11589cfea084f0e7feda4cf (patch) | |
tree | b6487e8ff7fb879bb9ee7d5f612cc61aa7ff00a5 /src/arch/arm/isa | |
parent | 1470dae8e949eaef8232dc621d9074329357265c (diff) | |
download | gem5-0916c376a97dacf5d11589cfea084f0e7feda4cf.tar.xz |
ARM: Differentiate between LDM exception return and LDM user regs.
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r-- | src/arch/arm/isa/formats/macromem.isa | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index 068b48199..c834c22cb 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -210,7 +210,9 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0); unsigned reg = 0; - bool forceUser = machInst.puswl.psruser; + bool force_user = machInst.puswl.psruser & !OPCODE_15; + bool exception_ret = machInst.puswl.psruser & OPCODE_15; + for (int i = 1; i < ones + 1; i++) { // Find the next register. while (!bits(regs, reg)) @@ -218,12 +220,12 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) replaceBits(regs, reg, 0); unsigned regIdx = reg; - if (forceUser) { + if (force_user) { regIdx = intRegForceUser(regIdx); } if (machInst.puswl.loadOp) { - if (reg == INTREG_PC && forceUser) { + if (reg == INTREG_PC && exception_ret) { // This must be the exception return form of ldm. microOps[i] = new MicroLdrRetUop(machInst, regIdx, INTREG_UREG0, addr); |