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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
commit3aa8faf1779ee71034c7a5d3ce2982e8e88834fc (patch)
treea6063668807e1178656fcd23c33c7f0129571c46 /src/arch/arm/isa
parentfaf6c727f6f206238eb6cbd4f6c84f6136c739a2 (diff)
downloadgem5-3aa8faf1779ee71034c7a5d3ce2982e8e88834fc.tar.xz
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/formats/misc.isa6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 7d58350a4..8d386b0b0 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -122,6 +122,12 @@ def format McrMrc15() {{
case MISCREG_BPIMVA:
return new WarnUnimplemented(
isRead ? "mrc bpimva" : "mcr bpimva", machInst);
+ case MISCREG_BPIALLIS:
+ return new WarnUnimplemented(
+ isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
+ case MISCREG_BPIALL:
+ return new WarnUnimplemented(
+ isRead ? "mrc bpiall" : "mcr bpiall", machInst);
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);