ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.

1 files changed, 6 insertions, 0 deletions

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 7d58350a4..8d386b0b0 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -122,6 +122,12 @@ def format McrMrc15() {{
           case MISCREG_BPIMVA:
             return new WarnUnimplemented(
                     isRead ? "mrc bpimva" : "mcr bpimva", machInst);
+          case MISCREG_BPIALLIS:
+            return new WarnUnimplemented(
+                    isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
+          case MISCREG_BPIALL:
+            return new WarnUnimplemented(
+                    isRead ? "mrc bpiall" : "mcr bpiall", machInst);
           default:
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);