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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:48 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:48 -0600 |
| commit | d63020717c8a722eb2f5236eacd042cdee78769d (patch) | |
| tree | f53db4e1a39979e80660a7c739f7046d6b8e72c2 /src/arch/arm/isa | |
| parent | 981e1dd7eea3661cc2a0f99e783459bdc9fe5bd9 (diff) | |
| download | gem5-d63020717c8a722eb2f5236eacd042cdee78769d.tar.xz | |
ARM: Adds dummy support for a L2 latency miscreg.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 6a734a582..3bcb5c97d 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -143,6 +143,9 @@ let {{ case MISCREG_BPIALL: return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); + case MISCREG_L2LATENCY: + return new WarnUnimplemented( + isRead ? "mrc l2latency" : "mcr l2latency", machInst); // Write only. case MISCREG_TLBIALLIS: |