ARM: Define versions of MSR and MRS outside the decoder.

4 files changed, 167 insertions, 0 deletions

diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 03849aaa1..72c2e559a 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -52,6 +52,7 @@ output header {{
 #include "arch/arm/insts/branch.hh"
 #include "arch/arm/insts/macromem.hh"
 #include "arch/arm/insts/mem.hh"
+#include "arch/arm/insts/misc.hh"
 #include "arch/arm/insts/mult.hh"
 #include "arch/arm/insts/pred_inst.hh"
 #include "arch/arm/insts/static_inst.hh"
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index df5fa2ad7..fafbc197d 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -55,3 +55,66 @@ let {{
     exec_output = PredOpExecute.subst(svcIop)
 
 }};
+
+let {{
+
+    header_output = decoder_output = exec_output = ""
+
+    mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
+    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
+                               { "code": mrsCpsrCode,
+                                 "predicate_test": predicateTest }, [])
+    header_output += MrsDeclare.subst(mrsCpsrIop)
+    decoder_output += MrsConstructor.subst(mrsCpsrIop)
+    exec_output += PredOpExecute.subst(mrsCpsrIop)
+
+    mrsSpsrCode = "Dest = Spsr"
+    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
+                               { "code": mrsSpsrCode,
+                                 "predicate_test": predicateTest }, [])
+    header_output += MrsDeclare.subst(mrsSpsrIop)
+    decoder_output += MrsConstructor.subst(mrsSpsrIop)
+    exec_output += PredOpExecute.subst(mrsSpsrIop)
+
+    msrCpsrRegCode = '''
+        uint32_t newCpsr =
+            cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
+        Cpsr = ~CondCodesMask & newCpsr;
+        CondCodes = CondCodesMask & newCpsr;
+    '''
+    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
+                                  { "code": msrCpsrRegCode,
+                                    "predicate_test": predicateTest }, [])
+    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
+    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
+    exec_output += PredOpExecute.subst(msrCpsrRegIop)
+
+    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
+    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
+                                  { "code": msrSpsrRegCode,
+                                    "predicate_test": predicateTest }, [])
+    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
+    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
+    exec_output += PredOpExecute.subst(msrSpsrRegIop)
+
+    msrCpsrImmCode = '''
+        uint32_t newCpsr =
+            cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
+        Cpsr = ~CondCodesMask & newCpsr;
+        CondCodes = CondCodesMask & newCpsr;
+    '''
+    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
+                                  { "code": msrCpsrImmCode,
+                                    "predicate_test": predicateTest }, [])
+    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
+    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
+    exec_output += PredOpExecute.subst(msrCpsrImmIop)
+
+    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
+    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
+                                  { "code": msrSpsrImmCode,
+                                    "predicate_test": predicateTest }, [])
+    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
+    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
+    exec_output += PredOpExecute.subst(msrSpsrImmIop)
+}};
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
new file mode 100644
index 000000000..a19228b3b
--- /dev/null
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -0,0 +1,100 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+def template MrsDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  protected:
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template MrsConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _dest)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template MsrRegDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  protected:
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template MsrRegConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _op1,
+                                          uint8_t mask)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template MsrImmDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  protected:
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template MsrImmConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          uint32_t imm,
+                                          uint8_t mask)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
+    {
+        %(constructor)s;
+    }
+}};
diff --git a/src/arch/arm/isa/templates/templates.isa b/src/arch/arm/isa/templates/templates.isa
index c4073e0a0..0ffa0e183 100644
--- a/src/arch/arm/isa/templates/templates.isa
+++ b/src/arch/arm/isa/templates/templates.isa
@@ -46,6 +46,9 @@
 //Templates for memory instructions
 ##include "mem.isa"
 
+//Miscellaneous instructions that don't fit elsewhere
+##include "misc.isa"
+
 //Templates for microcoded memory instructions
 ##include "macromem.isa"