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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:22 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:22 -0600
commitcdacbe734a9e6e0f20e0a37ef694995373b83f66 (patch)
tree775ea93dcd7acd5255818739ac78523634c8cc62 /src/arch/arm/isa
parentf4f5d03ed211571f07f13ea9d5df0d70f3101aa3 (diff)
downloadgem5-cdacbe734a9e6e0f20e0a37ef694995373b83f66.tar.xz
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path.
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/insts/ldr.isa27
1 files changed, 16 insertions, 11 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 92ad52a6d..b091da856 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -161,8 +161,13 @@ let {{
if self.user:
self.memFlags.append("ArmISA::TLB::UserMode")
- if self.flavor == "prefetch":
+ self.instFlags = []
+ if self.flavor == "dprefetch":
self.memFlags.append("Request::PREFETCH")
+ self.instFlags = ['IsDataPrefetch']
+ elif self.flavor == "iprefetch":
+ self.memFlags.append("Request::PREFETCH")
+ self.instFlags = ['IsInstPrefetch']
elif self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
elif self.flavor == "normal":
@@ -185,7 +190,7 @@ let {{
self.codeBlobs["ea_code"] = eaCode
# Code that actually handles the access
- if self.flavor == "prefetch":
+ if self.flavor == "dprefetch" or self.flavor == "iprefetch":
accCode = 'uint64_t temp = Mem%s; temp = temp;'
elif self.flavor == "fp":
accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
@@ -200,7 +205,7 @@ let {{
wbDecl = None
if self.writeback:
wbDecl = self.wbDecl
- self.emitHelper(base, wbDecl)
+ self.emitHelper(base, wbDecl, self.instFlags)
def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
@@ -325,11 +330,11 @@ let {{
RfeInst(mnem, False, False, True).emit()
RfeInst(mnem, False, False, False).emit()
- def buildPrefetches(mnem):
- LoadReg(mnem, False, False, False, size=1, flavor="prefetch").emit()
- LoadImm(mnem, False, False, False, size=1, flavor="prefetch").emit()
- LoadReg(mnem, False, True, False, size=1, flavor="prefetch").emit()
- LoadImm(mnem, False, True, False, size=1, flavor="prefetch").emit()
+ def buildPrefetches(mnem, type):
+ LoadReg(mnem, False, False, False, size=1, flavor=type).emit()
+ LoadImm(mnem, False, False, False, size=1, flavor=type).emit()
+ LoadReg(mnem, False, True, False, size=1, flavor=type).emit()
+ LoadImm(mnem, False, True, False, size=1, flavor=type).emit()
buildLoads("ldr")
buildLoads("ldrt", user=True)
@@ -346,9 +351,9 @@ let {{
buildRfeLoads("rfe")
- buildPrefetches("pld")
- buildPrefetches("pldw")
- buildPrefetches("pli")
+ buildPrefetches("pld", "dprefetch")
+ buildPrefetches("pldw", "dprefetch")
+ buildPrefetches("pli", "iprefetch")
LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit()
LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit()