diff options
| author | Min Kyu Jeong <MinKyu.Jeong@arm.com> | 2010-06-02 12:58:18 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <MinKyu.Jeong@arm.com> | 2010-06-02 12:58:18 -0500 |
| commit | 5d5bf8cbc7c0e388a1af80530601ec0422aab60a (patch) | |
| tree | 62b1b7809af4ea6974d21b6a3432750b5fa9c39f /src/arch/arm/isa | |
| parent | 4325519fc5d1cf2bf4e57edebc739b9f79446267 (diff) | |
| download | gem5-5d5bf8cbc7c0e388a1af80530601ec0422aab60a.tar.xz | |
ARM: Fix IT state not updating when an instruction memory instruction faults.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 4f1235b03..ea66ce2a6 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -342,6 +342,8 @@ def template LoadInitiateAcc {{ if (fault == NoFault) { fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); } + } else if (fault == NoFault && machInst.itstateMask != 0) { + xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); } return fault; |