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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
| commit | 6e39288be025b4608748d7f5613f6b3af54cc93b (patch) | |
| tree | 329c22e517ac130b9472266b5e972e8bd98b4364 /src/arch/arm/isa | |
| parent | e9c8f68c0fcfb72934b852a61671fb94a1927e1d (diff) | |
| download | gem5-6e39288be025b4608748d7f5613f6b3af54cc93b.tar.xz | |
ARM: Implement the bkpt instruction.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 6 | ||||
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
3 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index a1d0c53a2..e97769835 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -1167,7 +1167,7 @@ def format Thumb16Misc() {{ true, true, regList); } case 0xe: - return new WarnUnimplemented("bkpt", machInst); + return new BkptInst(machInst); case 0xf: if (bits(machInst, 3, 0) != 0) return new ItInst(machInst); diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index ddf548a19..64bff6cb1 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -456,6 +456,12 @@ let {{ decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) exec_output += PredOpExecute.subst(usada8Iop) + bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst", + "return new PrefetchAbort(PC, ArmFault::DebugEvent);") + header_output += BasicDeclare.subst(bkptIop) + decoder_output += BasicConstructor.subst(bkptIop) + exec_output += BasicExecute.subst(bkptIop) + nopIop = InstObjParams("nop", "NopInst", "PredOp", \ { "code" : "", "predicate_test" : predicateTest }) header_output += BasicDeclare.subst(nopIop) diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index b041cef43..0c52703e1 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -179,6 +179,7 @@ def operands {{ 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2), 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2), + 'PC': ('PC', 'ud', None, None, 2), 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, readNPC, writeNPC), 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, |