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authorDylan Johnson <Dylan.Johnson@ARM.com>2016-08-02 10:38:01 +0100
committerDylan Johnson <Dylan.Johnson@ARM.com>2016-08-02 10:38:01 +0100
commite727a0eeaa5f2d46921c8496d77623a9704d40b6 (patch)
tree3222bfcdd7e86d6c29fbb0fdcf69db276879b732 /src/arch/arm/isa
parentc20b6c56f68fe829965826dd0040bd1a1ddd76c7 (diff)
downloadgem5-e727a0eeaa5f2d46921c8496d77623a9704d40b6.tar.xz
arm: change instruction classes to catch hyp traps
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/formats/misc.isa9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index f81b96f2f..43a7cc975 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2013 ARM Limited
+// Copyright (c) 2010-2013,2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -181,15 +181,16 @@ let {{
switch (miscReg) {
case MISCREG_NOP:
- return new NopInst(machInst);
+ return new McrMrcMiscInst(isRead ? "mrc nop" : "mcr nop",
+ machInst, iss, MISCREG_NOP);
case MISCREG_CP15_UNIMPL:
return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
crn, opc1, crm, opc2, isRead ? "read" : "write"));
case MISCREG_DCCMVAC:
- return new FlushPipeInst(
- isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
+ return new McrMrcMiscInst(isRead ? "mrc dccmvac" : "mcr dccmvac",
+ machInst, iss, MISCREG_DCCMVAC);
case MISCREG_CP15ISB:
return new Isb(machInst, iss);
case MISCREG_CP15DSB: