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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-20 17:02:11 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-11-22 13:37:44 +0000 |
| commit | eac97c91da74acb602c580b36415ab4c6b08b582 (patch) | |
| tree | 88659a9023895c6cfbf2f01429aaa775b3d253ee /src/arch/arm/isa | |
| parent | e27ed32d9dcd7591c3a794fc1c9ca5b29ce0d91d (diff) | |
| download | gem5-eac97c91da74acb602c580b36415ab4c6b08b582.tar.xz | |
arch-arm: HVC instruction undefined in secure EL1
Since EL2 is not available in secure mode, any HVC call from secure mode
should be treated as undefined. This behaviour was implemented in
aarch32 HVC but not in 64 bit version
Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5921
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc64.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index 58f08f51e..00724c095 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -53,7 +53,7 @@ let {{ SCR scr = Scr64; if (!ArmSystem::haveVirtualization(xc->tcBase()) || - (ArmSystem::haveSecurity(xc->tcBase()) && !scr.hce)) { + (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { fault = disabledFault(); } else { fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5)); |