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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-09 17:52:37 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-29 10:17:47 +0000 |
| commit | f94f70237dfaac86c83dfbb7cb24e6a821b867eb (patch) | |
| tree | 31fd902bb76d6024e1eac46d301de40fb9db6ec9 /src/arch/arm/isa | |
| parent | 936b584ce35c079db98ab17c6ac9c6943ce7220e (diff) | |
| download | gem5-f94f70237dfaac86c83dfbb7cb24e6a821b867eb.tar.xz | |
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.
Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 14 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 20 |
2 files changed, 30 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 00bd0770f..722cd7415 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -377,6 +377,20 @@ namespace Aarch64 return new FailUnimplemented(read ? "mrs" : "msr", machInst, full_mnemonic); + } else if (miscReg == MISCREG_IMPDEF_UNIMPL) { + auto full_mnemonic = + csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", + read ? "mrs" : "msr", + op0, op1, crn, crm, op2); + + if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { + return new WarnUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic + " treated as NOP"); + } else { + return new FailUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic); + } + } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (miscReg == MISCREG_NZCV) { if (read) diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 4f1960b95..739741786 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -220,10 +220,22 @@ let {{ csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", crn, opc1, crm, opc2, isRead ? "read" : "write")); case MISCREG_IMPDEF_UNIMPL: - return new McrMrcImplDefined( - isRead ? "mrc implementation defined" : - "mcr implementation defined", - machInst, iss, MISCREG_IMPDEF_UNIMPL); + + if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { + auto mnemonic = + csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s", + crn, opc1, crm, opc2, isRead ? "read" : "write"); + + return new WarnUnimplemented( + isRead ? "mrc implementation defined" : + "mcr implementation defined", + machInst, mnemonic + " treated as NOP"); + } else { + return new McrMrcImplDefined( + isRead ? "mrc implementation defined" : + "mcr implementation defined", + machInst, iss, MISCREG_IMPDEF_UNIMPL); + } case MISCREG_CP15ISB: return new Isb(machInst, iss); case MISCREG_CP15DSB: |