SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.

8 files changed, 56 insertions, 100 deletions

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 03a585001..ffe5f45e3 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1103,7 +1103,6 @@ def format ArmMisc() {{
                 switch (IMM) {
                   case 0x0:
                     return new NopInst(machInst);
-#if FULL_SYSTEM
                   case 0x1:
                     return new YieldInst(machInst);
                   case 0x2:
@@ -1112,7 +1111,6 @@ def format ArmMisc() {{
                     return new WfiInst(machInst);
                   case 0x4:
                     return new SevInst(machInst);
-#endif
                   default:
                     return new Unknown(machInst);
                 }
diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa
index f532d828b..3b08acad7 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -42,35 +42,27 @@ def format M5ops() {{
     {
         const uint32_t m5func = bits(machInst, 23, 16);
         switch(m5func) {
-#if FULL_SYSTEM
             case 0x00: return new Arm(machInst);
             case 0x01: return new Quiesce(machInst);
             case 0x02: return new QuiesceNs(machInst);
             case 0x03: return new QuiesceCycles(machInst);
             case 0x04: return new QuiesceTime(machInst);
-#endif
             case 0x07: return new Rpns(machInst);
             case 0x09: return new WakeCPU(machInst);
             case 0x10: return new Deprecated_ivlb(machInst);
             case 0x11: return new Deprecated_ivle(machInst);
             case 0x20: return new Deprecated_exit (machInst);
             case 0x21: return new M5exit(machInst);
-#if FULL_SYSTEM
             case 0x31: return new Loadsymbol(machInst);
             case 0x30: return new Initparam(machInst);
-#endif
             case 0x40: return new Resetstats(machInst);
             case 0x41: return new Dumpstats(machInst);
             case 0x42: return new Dumpresetstats(machInst);
             case 0x43: return new M5checkpoint(machInst);
-#if FULL_SYSTEM
             case 0x50: return new M5readfile(machInst);
-#endif
             case 0x51: return new M5break(machInst);
             case 0x52: return new M5switchcpu(machInst);
-#if FULL_SYSTEM
             case 0x53: return new M5addsymbol(machInst);
-#endif
             case 0x54: return new M5panic(machInst);
             case 0x5a: return new M5workbegin(machInst);
             case 0x5b: return new M5workend(machInst);
diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa
index a0e0afd32..1c9a4b402 100644
--- a/src/arch/arm/isa/formats/unimp.isa
+++ b/src/arch/arm/isa/formats/unimp.isa
@@ -147,11 +147,10 @@ output exec {{
     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-#if FULL_SYSTEM
-        return new UndefinedInstruction;
-#else
-        return new UndefinedInstruction(machInst, false, mnemonic);
-#endif
+        if (FullSystem)
+            return new UndefinedInstruction;
+        else
+            return new UndefinedInstruction(machInst, false, mnemonic);
     }
 
     Fault
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index 8a94d1ebd..1ff6ef9e4 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -41,11 +41,10 @@ let {{
     sdivCode = '''
     if (Op2_sw == 0) {
         if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                return new UndefinedInstruction;
+            else
+                return new UndefinedInstruction(false, mnemonic);
         }
         Dest_sw = 0;
     } else if (Op1_sw == INT_MIN && Op2_sw == -1) {
@@ -65,11 +64,10 @@ let {{
     udivCode = '''
     if (Op2_uw == 0) {
         if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                return new UndefinedInstruction;
+            else
+                return new UndefinedInstruction(false, mnemonic);
         }
         Dest_uw = 0;
     } else {
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index e891a0a91..a157b414c 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -54,9 +54,7 @@ let {{
 
 
     armCode = '''
-#if FULL_SYSTEM
     PseudoInst::arm(xc->tcBase());
-#endif
     '''
     armIop = InstObjParams("arm", "Arm", "PredOp",
                            { "code": armCode,
@@ -67,9 +65,7 @@ let {{
     exec_output += PredOpExecute.subst(armIop)
 
     quiesceCode = '''
-#if FULL_SYSTEM
     PseudoInst::quiesce(xc->tcBase());
-#endif
     '''
     quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
                            { "code": quiesceCode,
@@ -80,9 +76,7 @@ let {{
     exec_output += QuiescePredOpExecute.subst(quiesceIop)
 
     quiesceNsCode = '''
-#if FULL_SYSTEM
     PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
-#endif
     '''
 
     quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
@@ -94,9 +88,7 @@ let {{
     exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
 
     quiesceCyclesCode = '''
-#if FULL_SYSTEM
     PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
-#endif
     '''
 
     quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
@@ -108,11 +100,9 @@ let {{
     exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
 
     quiesceTimeCode = '''
-#if FULL_SYSTEM
     uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
     R0 = bits(qt_val, 31, 0);
     R1 = bits(qt_val, 63, 32);
-#endif
     '''
 
     quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
@@ -188,9 +178,7 @@ let {{
     exec_output += PredOpExecute.subst(m5exitIop)
 
     loadsymbolCode = '''
-#if FULL_SYSTEM
     PseudoInst::loadsymbol(xc->tcBase());
-#endif
     '''
 
     loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
@@ -202,9 +190,7 @@ let {{
     exec_output += PredOpExecute.subst(loadsymbolIop)
 
     initparamCode = '''
-#if FULL_SYSTEM
     Rt = PseudoInst::initParam(xc->tcBase());
-#endif
     '''
 
     initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
@@ -260,11 +246,9 @@ let {{
     exec_output += PredOpExecute.subst(m5checkpointIop)
 
     m5readfileCode = '''
-#if FULL_SYSTEM
     int n = 4;
     uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
     R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
-#endif
     '''
     m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
                            { "code": m5readfileCode,
@@ -291,9 +275,7 @@ let {{
     exec_output += PredOpExecute.subst(m5switchcpuIop)
 
     m5addsymbolCode = '''
-#if FULL_SYSTEM
     PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
-#endif
     '''
     m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
                            { "code": m5addsymbolCode,
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 2cf54fcdb..495cb722c 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,11 +40,11 @@
 let {{
 
     svcCode = '''
-#if FULL_SYSTEM
-    fault = new SupervisorCall;
-#else
-    fault = new SupervisorCall(machInst);
-#endif
+    if (FullSystem) {
+        fault = new SupervisorCall;
+    } else {
+        fault = new SupervisorCall(machInst);
+    }
     '''
 
     svcIop = InstObjParams("svc", "Svc", "PredOp",
@@ -501,7 +501,6 @@ let {{
     exec_output += PredOpExecute.subst(yieldIop)
 
     wfeCode = '''
-#if FULL_SYSTEM
     // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
     if (SevMailbox == 1) {
         SevMailbox = 0;
@@ -511,14 +510,11 @@ let {{
     } else {
         PseudoInst::quiesce(xc->tcBase());
     }
-#endif
     '''
     wfePredFixUpCode = '''
-#if FULL_SYSTEM
     // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
     // and SEV interrupts
     SevMailbox = 1;
-#endif
     '''
     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
             { "code" : wfeCode,
@@ -530,14 +526,12 @@ let {{
     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
 
     wfiCode = '''
-#if FULL_SYSTEM
     // WFI doesn't sleep if interrupts are pending (masked or not)
     if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
         PseudoInst::quiesceSkip(xc->tcBase());
     } else {
         PseudoInst::quiesce(xc->tcBase());
     }
-#endif
     '''
     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
             { "code" : wfiCode, "predicate_test" : predicateTest },
@@ -547,7 +541,6 @@ let {{
     exec_output += QuiescePredOpExecute.subst(wfiIop)
 
     sevCode = '''
-#if FULL_SYSTEM
     SevMailbox = 1;
     System *sys = xc->tcBase()->getSystemPtr();
     for (int x = 0; x < sys->numContexts(); x++) {
@@ -560,7 +553,6 @@ let {{
             oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
         }
     }
-#endif
     '''
     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
             { "code" : sevCode, "predicate_test" : predicateTest },
@@ -577,11 +569,10 @@ let {{
     decoder_output += BasicConstructor.subst(itIop)
     exec_output += PredOpExecute.subst(itIop)
     unknownCode = '''
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(machInst, true);
-#endif
+    if (FullSystem)
+        return new UndefinedInstruction;
+    else
+        return new UndefinedInstruction(machInst, true);
     '''
     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
                                { "code": unknownCode,
@@ -634,12 +625,12 @@ let {{
 
     mrc15code = '''
     CPSR cpsr = Cpsr;
-    if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
-        return new UndefinedInstruction;
-#else
-        return new UndefinedInstruction(false, mnemonic);
-#endif
+    if (cpsr.mode == MODE_USER) {
+        if (FullSystem)
+            return new UndefinedInstruction;
+        else
+            return new UndefinedInstruction(false, mnemonic);
+    }
     Dest = MiscOp1;
     '''
 
@@ -653,12 +644,12 @@ let {{
 
     mcr15code = '''
     CPSR cpsr = Cpsr;
-    if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
-        return new UndefinedInstruction;
-#else
-        return new UndefinedInstruction(false, mnemonic);
-#endif
+    if (cpsr.mode == MODE_USER) {
+        if (FullSystem)
+            return new UndefinedInstruction;
+        else
+            return new UndefinedInstruction(false, mnemonic);
+    }
     MiscDest = Op1;
     '''
     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index fdb6237c0..9565ee14a 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -872,11 +872,10 @@ let {{
             readDestCode = 'destElem = gtoh(destReg.elements[i]);'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
-            fault = new UndefinedInstruction;
-#else
-            fault = new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                fault = new UndefinedInstruction;
+            else
+                fault = new UndefinedInstruction(false, mnemonic);
         } else {
             for (unsigned i = 0; i < eCount; i++) {
                 Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -927,11 +926,10 @@ let {{
             readDestCode = 'destElem = gtoh(destReg.elements[i]);'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
-            fault = new UndefinedInstruction;
-#else
-            fault = new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                fault = new UndefinedInstruction;
+            else
+                fault = new UndefinedInstruction(false, mnemonic);
         } else {
             for (unsigned i = 0; i < eCount; i++) {
                 Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -980,11 +978,10 @@ let {{
             readDestCode = 'destReg = destRegs[i];'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
-            fault = new UndefinedInstruction;
-#else
-            fault = new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                fault = new UndefinedInstruction;
+            else
+                fault = new UndefinedInstruction(false, mnemonic);
         } else {
             for (unsigned i = 0; i < rCount; i++) {
                 FloatReg srcReg1 = srcRegs1[i];
@@ -3298,14 +3295,14 @@ let {{
                 destReg.elements[i] = srcReg1.elements[index];
             } else {
                 index -= eCount;
-                if (index >= eCount)
-#if FULL_SYSTEM
-                    fault = new UndefinedInstruction;
-#else
-                    fault = new UndefinedInstruction(false, mnemonic);
-#endif
-                else
+                if (index >= eCount) {
+                    if (FullSystem)
+                        fault = new UndefinedInstruction;
+                    else
+                        fault = new UndefinedInstruction(false, mnemonic);
+                } else {
                     destReg.elements[i] = srcReg2.elements[index];
+                }
             }
         }
     '''
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index f319e75aa..b42a1c4b2 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -73,11 +73,10 @@ let {{
 
     swpPreAccCode = '''
         if (!((SCTLR)Sctlr).sw) {
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                return new UndefinedInstruction;
+            else
+                return new UndefinedInstruction(false, mnemonic);
         }
     '''