summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa
diff options
context:
space:
mode:
authoryuetsu.kodama <yuetsu.kodama@riken.jp>2018-10-20 11:58:54 +0900
committerAndreas Sandberg <andreas.sandberg@arm.com>2018-10-26 12:47:46 +0000
commit59e3585a84ef172eba57c9936680c0248f9a97db (patch)
tree8bf691977e16156e5d05d18c087cb2a77af19212 /src/arch/arm/isa
parentd4b3e064adeeace3c3e7d106801f95c14637c12f (diff)
downloadgem5-59e3585a84ef172eba57c9936680c0248f9a97db.tar.xz
arch-arm: We add PRFM PST instruction for arm
Note current PRFM supports only PLD, but PST (prefetch for store) is also important for latency hiding. We also bug fix in disassembler to display prfop correctly. Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13 Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp> Reviewed-on: https://gem5-review.googlesource.com/c/13675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/insts/ldr64.isa15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index 7c177263d..54e50d73e 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -74,6 +74,10 @@ let {{
elif self.flavor == "iprefetch":
self.memFlags.append("Request::PREFETCH")
self.instFlags = ['IsInstPrefetch']
+ elif self.flavor == "mprefetch":
+ self.memFlags.append("((((dest>>3)&3)==2)? \
+ (Request::PF_EXCLUSIVE):(Request::PREFETCH))")
+ self.instFlags = ['IsDataPrefetch']
if self.micro:
self.instFlags.append("IsMicroop")
@@ -176,7 +180,7 @@ let {{
self.buildEACode()
# Code that actually handles the access
- if self.flavor in ("dprefetch", "iprefetch"):
+ if self.flavor in ("dprefetch", "iprefetch", "mprefetch"):
accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
elif self.flavor == "fp":
if self.size in (1, 2, 4):
@@ -365,10 +369,11 @@ let {{
buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp")
buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp")
- LoadImm64("prfm", "PRFM64_IMM", 8, flavor="dprefetch").emit()
- LoadReg64("prfm", "PRFM64_REG", 8, flavor="dprefetch").emit()
- LoadLit64("prfm", "PRFM64_LIT", 8, literal=True, flavor="dprefetch").emit()
- LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="dprefetch").emit()
+ LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit()
+ LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit()
+ LoadLit64("prfm", "PRFM64_LIT", 8, literal=True,
+ flavor="mprefetch").emit()
+ LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit()
LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit()
LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit()