ARM: Cleanup implementation of ITSTATE and put important code in PCState.

Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.

9 files changed, 6 insertions, 124 deletions

diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 9af81b465..e8012ff89 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -245,7 +245,7 @@ let {{
             CondCodes = CondCodesMask & newCpsr;
             NextThumb = ((CPSR)newCpsr).t;
             NextJazelle = ((CPSR)newCpsr).j;
-            ForcedItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
+            NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
                 | (((CPSR)newCpsr).it1 & 0x3);
             '''
             buildImmDataInst(mnem + 's', code, flagType,
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 15879e0e3..28b140b93 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -94,7 +94,7 @@ let {{
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
         IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
-        ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
+        NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
                 | (((CPSR)Spsr).it1 & 0x3);
     '''
 
@@ -628,7 +628,7 @@ let {{
                     Cpsr = ~CondCodesMask & newCpsr;
                     NextThumb = ((CPSR)newCpsr).t;
                     NextJazelle = ((CPSR)newCpsr).j;
-                    ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC)
+                    NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
                                     | (((CPSR)URb).it1 & 0x3);
                     CondCodes = CondCodesMask & newCpsr;
                     '''
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index cf5c7b47a..35df88c81 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -83,10 +83,6 @@ let {{
         uint32_t newCpsr =
             cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
-        NextThumb = ((CPSR)newCpsr).t;
-        NextJazelle = ((CPSR)newCpsr).j;
-        ForcedItState = ((((CPSR)Op1).it2 << 2) & 0xFC)
-                | (((CPSR)Op1).it1 & 0x3);
         CondCodes = CondCodesMask & newCpsr;
     '''
     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
@@ -111,10 +107,6 @@ let {{
         uint32_t newCpsr =
             cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
-        NextThumb = ((CPSR)newCpsr).t;
-        NextJazelle = ((CPSR)newCpsr).j;
-        ForcedItState = ((((CPSR)imm).it2 << 2) & 0xFC)
-            | (((CPSR)imm).it1 & 0x3);
         CondCodes = CondCodesMask & newCpsr;
     '''
     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
@@ -538,7 +530,7 @@ let {{
     exec_output += PredOpExecute.subst(sevIop)
 
     itIop = InstObjParams("it", "ItInst", "PredOp", \
-            { "code" : "Itstate = machInst.newItstate;",
+            { "code" : ";",
               "predicate_test" : predicateTest },
             ["IsNonSpeculative", "IsSerializeAfter"])
     header_output += BasicDeclare.subst(itIop)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 20ce6df52..49a860213 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -217,7 +217,6 @@ def operands {{
 
     #Fixed index control regs
     'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
-    'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'),
     'Spsr': cntrlRegNC('MISCREG_SPSR'),
     'Fpsr': cntrlRegNC('MISCREG_FPSR'),
     'Fpsid': cntrlRegNC('MISCREG_FPSID'),
@@ -247,7 +246,8 @@ def operands {{
     'Thumb': pcStateReg('thumb', srtPC),
     'NextThumb': pcStateReg('nextThumb', srtMode),
     'NextJazelle': pcStateReg('nextJazelle', srtMode),
-    'ForcedItState': pcStateReg('forcedItState', srtMode),
+    'NextItState': pcStateReg('nextItstate', srtMode),
+    'Itstate': pcStateReg('itstate', srtMode),
 
     #Register operands depending on a field in the instruction encoding. These
     #should be avoided since they may not be portable across different
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index a7f7f0da8..a62dec5cf 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -241,10 +241,6 @@ def template MicroNeonMixExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index f26ee55e8..43a742242 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -102,11 +102,6 @@ def template SwapExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -135,11 +130,6 @@ def template SwapInitiateAcc {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -166,10 +156,6 @@ def template SwapCompleteAcc {{
             }
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -199,11 +185,6 @@ def template LoadExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -238,11 +219,6 @@ def template NeonLoadExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -276,11 +252,6 @@ def template StoreExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -319,11 +290,6 @@ def template NeonStoreExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -363,11 +329,6 @@ def template StoreExExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -396,10 +357,6 @@ def template StoreExInitiateAcc {{
         } else {
             xc->setPredicate(false);
         }
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
 
         return fault;
     }
@@ -430,11 +387,6 @@ def template StoreInitiateAcc {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -467,11 +419,6 @@ def template NeonStoreInitiateAcc {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0 &&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -494,10 +441,6 @@ def template LoadInitiateAcc {{
             }
         } else {
             xc->setPredicate(false);
-            if (fault == NoFault && machInst.itstateMask != 0 &&
-                    (!isMicroop() || isLastMicroop())) {
-                xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-            }
         }
 
         return fault;
@@ -523,10 +466,6 @@ def template NeonLoadInitiateAcc {{
             }
         } else {
             xc->setPredicate(false);
-            if (fault == NoFault && machInst.itstateMask != 0 &&
-                   (!isMicroop() || isLastMicroop())) {
-                xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-            }
         }
 
         return fault;
@@ -557,10 +496,6 @@ def template LoadCompleteAcc {{
             }
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -591,10 +526,6 @@ def template NeonLoadCompleteAcc {{
             }
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -604,10 +535,6 @@ def template StoreCompleteAcc {{
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        if (machInst.itstateMask != 0) {
-            warn_once("Complete acc isn't called on normal stores in O3.");
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
         return NoFault;
     }
 }};
@@ -618,10 +545,6 @@ def template NeonStoreCompleteAcc {{
             PacketPtr pkt, %(CPU_exec_context)s *xc,
             Trace::InstRecord *traceData) const
     {
-        if (machInst.itstateMask != 0) {
-            warn_once("Complete acc isn't called on normal stores in O3.");
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
         return NoFault;
     }
 }};
@@ -646,10 +569,6 @@ def template StoreExCompleteAcc {{
             }
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 0347869f8..694dc46da 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -438,9 +438,6 @@ def template ClrexInitiateAcc {{
             }
         } else {
             xc->setPredicate(false);
-            if (fault == NoFault && machInst.itstateMask != 0) {
-                xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-            }
         }
 
         return fault;
@@ -452,10 +449,6 @@ def template ClrexCompleteAcc {{
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        if (machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return NoFault;
     }
 }};
diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index 2e88c9333..fe3a026b8 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -229,10 +229,6 @@ def template NeonEqualRegExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -281,10 +277,6 @@ def template NeonUnequalRegExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 95c7c8e1b..4ab1335e0 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -174,11 +174,6 @@ def template PredOpExecute {{
             xc->setPredicate(false);
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0&&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};
@@ -206,11 +201,6 @@ def template QuiescePredOpExecute {{
 #endif
         }
 
-        if (fault == NoFault && machInst.itstateMask != 0&&
-                (!isMicroop() || isLastMicroop())) {
-            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
-        }
-
         return fault;
     }
 }};