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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-24 16:21:41 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-26 09:45:47 +0000 |
| commit | f5c8fc6bbedfe62bcb9514568b8ee13e073c807b (patch) | |
| tree | 3a140bbf83c79635c15c20c29ed8673dfd978601 /src/arch/arm/isa | |
| parent | 68bc5397c937c7289ad7e78416132dc77ccf34a9 (diff) | |
| download | gem5-f5c8fc6bbedfe62bcb9514568b8ee13e073c807b.tar.xz | |
arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.
Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13779
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 26c65ec8f..3f4e33711 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -446,13 +446,13 @@ namespace Aarch64 read ? "mrs" : "msr", op0, op1, crn, crm, op2); - if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { - return new WarnUnimplemented(read ? "mrs" : "msr", - machInst, full_mnemonic + " treated as NOP"); - } else { - return new FailUnimplemented(read ? "mrs" : "msr", - machInst, full_mnemonic); - } + uint32_t iss = msrMrs64IssBuild( + read, op0, op1, crn, crm, op2, rt); + + return new MiscRegImplDefined64( + read ? "mrs" : "msr", + machInst, miscReg, read, iss, full_mnemonic, + miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]); } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (miscReg == MISCREG_NZCV) { |