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authorAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:20:20 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:20:20 -0500
commitfe3d790ac8da41e8a0b9af93510cd874585c37e7 (patch)
tree66f8eefdbe593efcb4de351eda697afc76e1e7c8 /src/arch/arm/isa
parent845f791f377001bf348d8f99798d4b1b6fb5d581 (diff)
downloadgem5-fe3d790ac8da41e8a0b9af93510cd874585c37e7.tar.xz
ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/insts/m5ops.isa6
-rw-r--r--src/arch/arm/isa/insts/misc.isa20
-rw-r--r--src/arch/arm/isa/templates/pred.isa32
3 files changed, 48 insertions, 10 deletions
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index da3609bbc..8521cbc97 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -66,7 +66,7 @@ let {{
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceIop)
decoder_output += BasicConstructor.subst(quiesceIop)
- exec_output += PredOpExecute.subst(quiesceIop)
+ exec_output += QuiescePredOpExecute.subst(quiesceIop)
quiesceNsCode = '''
#if FULL_SYSTEM
@@ -80,7 +80,7 @@ let {{
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceNsIop)
decoder_output += BasicConstructor.subst(quiesceNsIop)
- exec_output += PredOpExecute.subst(quiesceNsIop)
+ exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
quiesceCyclesCode = '''
#if FULL_SYSTEM
@@ -94,7 +94,7 @@ let {{
["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
header_output += BasicDeclare.subst(quiesceCyclesIop)
decoder_output += BasicConstructor.subst(quiesceCyclesIop)
- exec_output += PredOpExecute.subst(quiesceCyclesIop)
+ exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
quiesceTimeCode = '''
#if FULL_SYSTEM
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index be51d927d..cf5c7b47a 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -491,10 +491,13 @@ let {{
wfeCode = '''
#if FULL_SYSTEM
- if (SevMailbox)
+ if (SevMailbox) {
SevMailbox = 0;
- else
+ PseudoInst::quiesceSkip(xc->tcBase());
+ }
+ else {
PseudoInst::quiesce(xc->tcBase());
+ }
#endif
'''
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
@@ -502,7 +505,7 @@ let {{
["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
header_output += BasicDeclare.subst(wfeIop)
decoder_output += BasicConstructor.subst(wfeIop)
- exec_output += PredOpExecute.subst(wfeIop)
+ exec_output += QuiescePredOpExecute.subst(wfeIop)
wfiCode = '''
#if FULL_SYSTEM
@@ -511,22 +514,25 @@ let {{
'''
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
- ["IsNonSpeculative", "IsQuiesce"])
+ ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
header_output += BasicDeclare.subst(wfiIop)
decoder_output += BasicConstructor.subst(wfiIop)
- exec_output += PredOpExecute.subst(wfiIop)
+ exec_output += QuiescePredOpExecute.subst(wfiIop)
sevCode = '''
// Need a way for O3 to not scoreboard these accesses as pipe flushes.
+ SevMailbox = 1;
System *sys = xc->tcBase()->getSystemPtr();
for (int x = 0; x < sys->numContexts(); x++) {
ThreadContext *oc = sys->getThreadContext(x);
- oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ if (oc != xc->tcBase()) {
+ oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ }
}
'''
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
{ "code" : sevCode, "predicate_test" : predicateTest },
- ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+ ["IsNonSpeculative", "IsSquashAfter"])
header_output += BasicDeclare.subst(sevIop)
decoder_output += BasicConstructor.subst(sevIop)
exec_output += PredOpExecute.subst(sevIop)
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index c9e7b1803..2a4bd9dab 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -170,6 +170,38 @@ def template PredOpExecute {{
}
}};
+def template QuiescePredOpExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ uint64_t resTemp = 0;
+ resTemp = resTemp;
+ %(op_decl)s;
+ %(op_rd)s;
+
+ if (%(predicate_test)s)
+ {
+ %(code)s;
+ if (fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ } else {
+ xc->setPredicate(false);
+#if FULL_SYSTEM
+ PseudoInst::quiesceSkip(xc->tcBase());
+#endif
+ }
+
+ if (fault == NoFault && machInst.itstateMask != 0&&
+ (!isMicroop() || isLastMicroop())) {
+ xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+ }
+
+ return fault;
+ }
+}};
+
def template DataDecode {{
if (machInst.opcode4 == 0) {
if (machInst.sField == 0)