arch: Stop using TheISA within the ISAs.

We know for sure what the ISA is, so there's no need for the
indirection.

Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

5 files changed, 31 insertions, 31 deletions

diff --git a/src/arch/arm/isa/insts/fp64.isa b/src/arch/arm/isa/insts/fp64.isa
index 26803e7e5..7decbac25 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -45,7 +45,7 @@ let {{
     exec_output = ""
 
     zeroSveVecRegUpperPartCode = '''
-        TheISA::ISA::zeroSveVecRegUpperPart(%s,
+        ArmISA::ISA::zeroSveVecRegUpperPart(%s,
             ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
     '''
 
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index fe7eaf0f8..56112a7c1 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -185,7 +185,7 @@ let {{
                 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
             elif self.flavor == "fp":
                 accEpilogCode = '''
-                    TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+                    ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
                         ArmStaticInst::getCurSveVecLen<uint64_t>(
                             xc->tcBase()));
                 '''
@@ -239,10 +239,10 @@ let {{
             # Code that actually handles the access
             if self.flavor == "fp":
                 accEpilogCode = '''
-                    TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+                    ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
                         ArmStaticInst::getCurSveVecLen<uint64_t>(
                             xc->tcBase()));
-                    TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
+                    ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
                         ArmStaticInst::getCurSveVecLen<uint64_t>(
                             xc->tcBase()));
                 '''
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa b/src/arch/arm/isa/insts/neon64_mem.isa
index 8f53369e9..03ad29409 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -45,7 +45,7 @@ let {{
     exec_output = ''
 
     zeroSveVecRegUpperPartCode = '''
-        TheISA::ISA::zeroSveVecRegUpperPart(%s,
+        ArmISA::ISA::zeroSveVecRegUpperPart(%s,
             ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
     '''
 
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index e5e9e2450..c46a34da4 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1555,7 +1555,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -1616,7 +1616,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto tmpVec = tmpVecC.as<Element>();
         int ePow2Count = 1;
         while (ePow2Count < eCount) {
@@ -1761,7 +1761,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp2 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; i++) {
             auxOp2[i] = AA64FpOp2_ud[i];
@@ -1917,7 +1917,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; i++) {
             auxGpOp[i] = GpOp_x[i];
@@ -1981,7 +1981,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto tmpPred = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             tmpPred[i] = GpOp_x[i];
@@ -2140,7 +2140,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto tmpPred = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             tmpPred[i] = GpOp_x[i];
@@ -2185,7 +2185,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto tmpPred = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             tmpPred[i] = GpOp_x[i];
@@ -2268,7 +2268,7 @@ let {{
         unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
                 xc->tcBase());
         bool dobreak = false;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxGpOp[i] = GpOp_ub[i];
@@ -2320,7 +2320,7 @@ let {{
         unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
                 xc->tcBase());
         bool last = POp1_ub.lastActive(GpOp_ub, eCount);
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxGpOp[i] = GpOp_ub[i];
@@ -2458,7 +2458,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxGpOp[i] = GpOp_x[i];
@@ -2500,7 +2500,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             auxGpOp[i] = GpOp_x[i];
@@ -2568,14 +2568,14 @@ let {{
         if unpackHalf == Unpack.Low:
             if regType == SrcRegType.Predicate:
                 code += '''
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPOp1 = tmpPredC.as<SElement>();
         for (int i = 0; i < eCount; ++i) {
             auxPOp1[i] = POp1_xs[i];
         }'''
             else:
                 code += '''
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<SElement>();
         for (int i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_xs[i];
@@ -2636,7 +2636,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -2707,7 +2707,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -2736,7 +2736,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         int firstelem = -1, lastelem = -2;
         for (int i = 0; i < eCount; ++i) {
@@ -2799,7 +2799,7 @@ let {{
                 xc->tcBase());'''
         if srcType == SrcRegType.Predicate:
             code += '''
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPOp1 = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             uint8_t v = POp1_x.get_raw(i);
@@ -2808,7 +2808,7 @@ let {{
         PDest_x[0] = 0;'''
         else:
             code += '''
-        TheISA::VecRegContainer tmpRegC;
+        ArmISA::VecRegContainer tmpRegC;
         auto auxOp1 = tmpRegC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -4464,7 +4464,7 @@ let {{
         constexpr unsigned sz = sizeof(Element);
         int s;
         int part = %d;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPDest = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = 2 * i + part;
@@ -4485,7 +4485,7 @@ let {{
     trnIterCode = '''
         int s;
         int part = %d;
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = 2 * i + part;
@@ -4681,7 +4681,7 @@ let {{
         constexpr unsigned sz = sizeof(Element);
         int s;
         int part = %d;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPDest = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount; i++) {
             s = 2 * i + part;
@@ -4705,7 +4705,7 @@ let {{
     uzpIterCode = '''
         int s;
         int part = %d;
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; i++) {
             s = 2 * i + part;
@@ -4766,7 +4766,7 @@ let {{
         constexpr unsigned sz = sizeof(Element);
         int s;
         int part = %d;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPDest = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = i + (part * (eCount / 2));
@@ -4787,7 +4787,7 @@ let {{
     zipIterCode = '''
         int s;
         int part = %d;
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = i + (part * (eCount / 2));
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 0f656dac9..0a0469acc 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -51,12 +51,12 @@ def operand_types {{
     'tud' : 'std::array<uint64_t, 2>',
     'sf' : 'float',
     'df' : 'double',
-    'vc' : 'TheISA::VecRegContainer',
+    'vc' : 'ArmISA::VecRegContainer',
     # For operations that are implemented as a template
     'x' : 'TPElem',
     'xs' : 'TPSElem',
     'xd' : 'TPDElem',
-    'pc' : 'TheISA::VecPredRegContainer',
+    'pc' : 'ArmISA::VecPredRegContainer',
     'pb' : 'uint8_t'
 }};