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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:48:44 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:48:44 -0700 |
| commit | 4415e2dcd6ca508c4ffa8aa1fdcc53daee79b898 (patch) | |
| tree | 9aed3ec43297f15e678d875eb003d26940d311e6 /src/arch/arm/isa | |
| parent | 7d4ef8a398343800819930df97fcd79f7a9ba099 (diff) | |
| download | gem5-4415e2dcd6ca508c4ffa8aa1fdcc53daee79b898.tar.xz | |
ARM: Get rid of unnecessary Re operand.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/bitfields.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
2 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa index bcb2869b7..e334f5521 100644 --- a/src/arch/arm/isa/bitfields.isa +++ b/src/arch/arm/isa/bitfields.isa @@ -70,8 +70,6 @@ def bitfield SHIFT_SIZE <11: 7>; def bitfield SHIFT < 6: 5>; def bitfield RM < 3: 0>; -def bitfield RE <20:16>; - def bitfield RS <11: 8>; def bitfield RDUP <19:16>; diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index f82e49109..be4ec6e03 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -46,7 +46,6 @@ def operands {{ 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3), 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4), - 'Re': ('IntReg', 'uw', 'RE', 'IsInteger', 5), 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5), 'R0': ('IntReg', 'uw', '0', 'IsInteger', 5), |