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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:02 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:02 -0500 |
| commit | c02f9cdddf157b91ca3a338bbe8b2a2b68d4ee93 (patch) | |
| tree | 71d3c04ca37529509208fad63567cdbc61c1c29b /src/arch/arm/isa | |
| parent | 1e7b317a988f5c23a828204451d567055f11afe3 (diff) | |
| download | gem5-c02f9cdddf157b91ca3a338bbe8b2a2b68d4ee93.tar.xz | |
ARM: Add new base classes for data processing instructions.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index f5d3e1042..244d217ce 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -76,6 +76,12 @@ def operands {{ maybePCRead, maybePCWrite), 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, + maybePCRead, maybePCWrite), + 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, + maybePCRead, maybePCWrite), + 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, + maybePCRead, maybePCWrite), #General Purpose Integer Reg Operands 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), |