diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
| commit | dc8018a5c3482008232e6faaa2d96cf20aed7485 (patch) | |
| tree | a972ac4544e227397595baf6eeb30e1854f480fc /src/arch/arm/isa | |
| parent | c8c82f09a282832d919f7eb073a47be838e65b29 (diff) | |
| download | gem5-dc8018a5c3482008232e6faaa2d96cf20aed7485.tar.xz | |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/bitfields.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/pred.isa | 16 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa index fc4b97984..ba9a39efb 100644 --- a/src/arch/arm/isa/bitfields.isa +++ b/src/arch/arm/isa/bitfields.isa @@ -65,7 +65,7 @@ def bitfield OPCODE_18 opcode18; def bitfield OPCODE_15_12 opcode15_12; def bitfield OPCODE_15 opcode15; def bitfield MISC_OPCODE miscOpcode; -def bitfield OPC2 opc2; +def bitfield OPC2 opc2; def bitfield OPCODE_7 opcode7; def bitfield OPCODE_6 opcode6; def bitfield OPCODE_4 opcode4; diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index b9745e8ba..8d254f571 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -41,7 +41,7 @@ // Authors: Stephen Hines let {{ - + calcCcCode = ''' if (%(canOverflow)s){ cprintf("canOverflow: %%d\\n", Rd < resTemp); @@ -52,7 +52,7 @@ let {{ _iz = (resTemp == 0); _iv = %(ivValue)s; _ic = %(icValue)s; - + CondCodesNZ = (_in << 1) | (_iz); CondCodesC = _ic; CondCodesV = _iv; @@ -79,7 +79,7 @@ let {{ iv = 'CondCodesV' negBit = 63 elif flagtype == "overflow": - canOverflow = "true" + canOverflow = "true" icReg = icImm = iv = '0' elif flagtype == "add": icReg = icImm = 'findCarry(32, resTemp, Rn, op2)' @@ -94,12 +94,12 @@ let {{ icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)' icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)' iv = 'CondCodesV' - return (calcCcCode % {"icValue" : icReg, - "ivValue" : iv, + return (calcCcCode % {"icValue" : icReg, + "ivValue" : iv, "negBit" : negBit, "canOverflow" : canOverflow }, - calcCcCode % {"icValue" : icImm, - "ivValue" : iv, + calcCcCode % {"icValue" : icImm, + "ivValue" : iv, "negBit" : negBit, "canOverflow" : canOverflow }) @@ -116,7 +116,7 @@ let {{ negBit = 63 elif flagtype == "overflow": icVaule = ivValue = '0' - canOverflow = "true" + canOverflow = "true" elif flagtype == "add": icValue = 'findCarry(32, resTemp, Rn, rotated_imm)' ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)' |