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authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:16 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:16 -0500
commitb8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 (patch)
tree273490f7ecbdbf3dc6f89d3ef46c46c7f07bc24c /src/arch/arm/isa_traits.hh
parent3aea20d143ee27e0562f6f9ea3d4c1b4bbfd20f3 (diff)
downloadgem5-b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3.tar.xz
ARM: Implement ARM CPU interrupts
Diffstat (limited to 'src/arch/arm/isa_traits.hh')
-rw-r--r--src/arch/arm/isa_traits.hh10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 4cffe3bec..d81981ff7 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -110,6 +110,7 @@ namespace ArmISA
const int LogVMPageSize = 12; // 4K bytes
const int VMPageSize = (1 << LogVMPageSize);
+ // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
const int MachineBytes = 4;
@@ -122,6 +123,15 @@ namespace ArmISA
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
+ enum InterruptTypes
+ {
+ INT_RST,
+ INT_ABT,
+ INT_IRQ,
+ INT_FIQ,
+ NumInterruptTypes
+ };
+
// These otherwise unused bits of the PC are used to select a mode
// like the J and T bits of the CPSR.
static const Addr PcJBitShift = 33;