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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-18 13:19:49 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-10 10:15:05 +0000 |
commit | 3a5ff476ffdcfcef2a6d0427d9add590984596e7 (patch) | |
tree | 6e3992c2a60ddeea4322b1f9ac04800de37de5e7 /src/arch/arm/kvm/armv8_cpu.cc | |
parent | 55a10a13f93ed5bbc12790bfcbdfbbf1975f0211 (diff) | |
download | gem5-3a5ff476ffdcfcef2a6d0427d9add590984596e7.tar.xz |
arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)
Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/kvm/armv8_cpu.cc')
-rw-r--r-- | src/arch/arm/kvm/armv8_cpu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc index 2ac97441d..cff138ce4 100644 --- a/src/arch/arm/kvm/armv8_cpu.cc +++ b/src/arch/arm/kvm/armv8_cpu.cc @@ -51,7 +51,7 @@ static_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs."); // The KVM interface accesses vector registers of 4 single precision // floats instead of individual registers. -constexpr static unsigned NUM_QREGS = NumFloatV8ArchRegs / 4; +constexpr static unsigned NUM_QREGS = NumVecV8ArchRegs; static_assert(NUM_QREGS == 32, "Unexpected number of aarch64 vector regs."); #define EXTRACT_FIELD(v, name) \ |