kvm, arm, dev: Add an in-kernel GIC implementation

This changeset adds a GIC implementation that uses the kernel's
built-in support for simulating the interrupt controller. Since there
is currently no support for state transfer between gem5 and the
kernel, the device model does not support serialization and CPU
switching (which would require switching to a gem5-simulated GIC).

4 files changed, 338 insertions, 0 deletions

diff --git a/src/arch/arm/kvm/KvmGic.py b/src/arch/arm/kvm/KvmGic.py
new file mode 100644
index 000000000..53814698e
--- /dev/null
+++ b/src/arch/arm/kvm/KvmGic.py
@@ -0,0 +1,54 @@
+# Copyright (c) 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.proxy import *
+
+from Gic import BaseGic
+from KvmVM import KvmVM
+from System import System
+
+class KvmGic(BaseGic):
+    type = 'KvmGic'
+    cxx_header = "arch/arm/kvm/gic.hh"
+
+    dist_addr = Param.Addr(0x1f001000, "Address for distributor")
+    cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
+
+    system = Param.System(Parent.any,
+                          'System this interrupt controller belongs to')
+    kvmVM = Param.KvmVM(Parent.any, 'KVM VM (i.e., shared memory domain)')
diff --git a/src/arch/arm/kvm/SConscript b/src/arch/arm/kvm/SConscript
index 50589659c..185aac7b6 100644
--- a/src/arch/arm/kvm/SConscript
+++ b/src/arch/arm/kvm/SConscript
@@ -45,6 +45,9 @@ if not (env['USE_KVM'] and env['TARGET_ISA'] == 'arm'):
 import platform
 host_isa = platform.machine()
 
+SimObject('KvmGic.py')
+Source('gic.cc')
+
 if host_isa == "armv7l":
     SimObject('ArmKvmCPU.py')
     Source('arm_cpu.cc')
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
new file mode 100644
index 000000000..9010d8df8
--- /dev/null
+++ b/src/arch/arm/kvm/gic.cc
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "arch/arm/kvm/gic.hh"
+
+#include <linux/kvm.h>
+
+#include "debug/Interrupt.hh"
+#include "params/KvmGic.hh"
+
+KvmGic::KvmGic(const KvmGicParams *p)
+    : BaseGic(p),
+      system(*p->system),
+      vm(*p->kvmVM),
+      kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2)),
+      distRange(RangeSize(p->dist_addr, KVM_VGIC_V2_DIST_SIZE)),
+      cpuRange(RangeSize(p->cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
+      addrRanges{distRange, cpuRange}
+{
+    kdev.setAttr<uint64_t>(
+        KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST,
+        p->dist_addr);
+    kdev.setAttr<uint64_t>(
+        KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU,
+        p->cpu_addr);
+}
+
+KvmGic::~KvmGic()
+{
+}
+
+void
+KvmGic::serialize(std::ostream &os)
+{
+    panic("Checkpointing unsupported\n");
+}
+
+void
+KvmGic::unserialize(Checkpoint *cp, const std::string &sec)
+{
+    panic("Checkpointing unsupported\n");
+}
+
+Tick
+KvmGic::read(PacketPtr pkt)
+{
+    panic("KvmGic: PIO from gem5 is currently unsupported\n");
+}
+
+Tick
+KvmGic::write(PacketPtr pkt)
+{
+    panic("KvmGic: PIO from gem5 is currently unsupported\n");
+}
+
+void
+KvmGic::sendInt(uint32_t num)
+{
+    DPRINTF(Interrupt, "Set SPI %d\n", num);
+    setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, true);
+}
+
+void
+KvmGic::clearInt(uint32_t num)
+{
+    DPRINTF(Interrupt, "Clear SPI %d\n", num);
+    setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, num, false);
+}
+
+void
+KvmGic::sendPPInt(uint32_t num, uint32_t cpu)
+{
+    DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
+    setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, true);
+}
+
+void
+KvmGic::clearPPInt(uint32_t num, uint32_t cpu)
+{
+    DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
+    setIntState(KVM_ARM_IRQ_TYPE_PPI, cpu, num, false);
+}
+
+void
+KvmGic::verifyMemoryMode() const
+{
+    if (!(system.isAtomicMode() && system.bypassCaches())) {
+        fatal("The in-kernel KVM GIC can only be used with KVM CPUs, but the "
+              "current memory mode does not support KVM.\n");
+    }
+}
+
+void
+KvmGic::setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high)
+{
+    assert(type < KVM_ARM_IRQ_TYPE_MASK);
+    assert(vcpu < KVM_ARM_IRQ_VCPU_MASK);
+    assert(irq < KVM_ARM_IRQ_NUM_MASK);
+    const uint32_t line(
+        (type << KVM_ARM_IRQ_TYPE_SHIFT) |
+        (vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
+        (irq << KVM_ARM_IRQ_NUM_SHIFT));
+
+    vm.setIRQLine(line, high);
+}
+
+
+KvmGic *
+KvmGicParams::create()
+{
+    return new KvmGic(this);
+}
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
new file mode 100644
index 000000000..3b196d108
--- /dev/null
+++ b/src/arch/arm/kvm/gic.hh
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#ifndef __ARCH_ARM_KVM_GIC_HH__
+#define __ARCH_ARM_KVM_GIC_HH__
+
+#include "arch/arm/system.hh"
+#include "cpu/kvm/device.hh"
+#include "cpu/kvm/vm.hh"
+#include "dev/arm/base_gic.hh"
+#include "dev/platform.hh"
+
+class KvmGicParams;
+
+/**
+ * In-kernel GIC model.
+ *
+ * When using a KVM-based CPU model, it is possible to offload GIC
+ * emulation to the kernel. This reduces some overheads when the guest
+ * accesses the GIC and makes it possible to use in-kernel
+ * architected/generic timer emulation.
+ *
+ * This device uses interfaces with the kernel GicV2 model that is
+ * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
+ * Linux kernel sources.
+ *
+ * This GIC model has the following known limitations:
+ * <ul>
+ *   <li>Checkpointing is not supported.
+ *   <li>This model only works with kvm. Simulated CPUs are not
+ *       supported since this would require the kernel to inject
+ *       interrupt into the simulated CPU.
+ * </ul>
+ *
+ * @warn This GIC model cannot be used with simulated CPUs!
+ */
+class KvmGic : public BaseGic
+{
+  public: // SimObject / Serializable / Drainable
+    KvmGic(const KvmGicParams *p);
+    ~KvmGic();
+
+    void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+    void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+
+    void serialize(std::ostream &os) M5_ATTR_OVERRIDE;
+    void unserialize(Checkpoint *cp, const std::string &sec)  M5_ATTR_OVERRIDE;
+
+  public: // PioDevice
+    AddrRangeList getAddrRanges() const { return addrRanges; }
+    Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
+    Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+
+  public: // BaseGic
+    void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
+    void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
+
+    void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+    void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+
+  protected:
+    /**
+     * Do memory mode sanity checks
+     *
+     * This method only really exists to warn users that try to switch
+     * to a simulate CPU. There is no fool proof method to detect
+     * simulated CPUs, but checking that we're in atomic mode and
+     * bypassing caches should be robust enough.
+     */
+    void verifyMemoryMode() const;
+
+    /**
+     * Update the kernel's VGIC interrupt state
+     *
+     * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI)
+     * @param vcpu CPU id within KVM (ignored for SPIs)
+     * @param irq Interrupt number
+     * @param high True to signal an interrupt, false to clear it.
+     */
+    void setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high);
+
+    /** System this interrupt controller belongs to */
+    System &system;
+    /** VM for this system */
+    KvmVM &vm;
+    /** Kernel interface to the GIC */
+    KvmDevice kdev;
+
+    /** Address range for the distributor interface */
+    const AddrRange distRange;
+    /** Address range for the CPU interfaces */
+    const AddrRange cpuRange;
+    /** Union of all memory  */
+    const AddrRangeList addrRanges;
+};
+
+#endif // __ARCH_ARM_KVM_GIC_HH__