ARM: Mark some variables uncacheable until boot all CPUs are enabled.

There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).

1 files changed, 21 insertions, 0 deletions

diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index 445fa2f19..66f4f26af 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -117,6 +117,27 @@ LinuxArmSystem::LinuxArmSystem(Params *p)
     } else {
         panic("couldn't find kernel symbol \'udelay\'");
     }
+
+    secDataPtrAddr = 0;
+    secDataAddr = 0;
+    penReleaseAddr = 0;
+    kernelSymtab->findAddress("__secondary_data", secDataPtrAddr);
+    kernelSymtab->findAddress("secondary_data", secDataAddr);
+    kernelSymtab->findAddress("pen_release", penReleaseAddr);
+
+    secDataPtrAddr &= ~ULL(0x7F);
+    secDataAddr &= ~ULL(0x7F);
+    penReleaseAddr &= ~ULL(0x7F);
+}
+
+bool
+LinuxArmSystem::adderBootUncacheable(Addr a)
+{
+    Addr block = a & ~ULL(0x7F);
+    if (block == secDataPtrAddr || block == secDataAddr ||
+            block == penReleaseAddr)
+        return true;
+    return false;
 }
 
 void