ARM: Mark some variables uncacheable until boot all CPUs are enabled.

There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).

1 files changed, 11 insertions, 0 deletions

diff --git a/src/arch/arm/linux/system.hh b/src/arch/arm/linux/system.hh
index 2ef65fea2..54681096b 100644
--- a/src/arch/arm/linux/system.hh
+++ b/src/arch/arm/linux/system.hh
@@ -69,6 +69,8 @@ class LinuxArmSystem : public ArmSystem
 
     void initState();
 
+    bool adderBootUncacheable(Addr a);
+
   private:
 #ifndef NDEBUG
     /** Event to halt the simulator if the kernel calls panic()  */
@@ -87,6 +89,15 @@ class LinuxArmSystem : public ArmSystem
      * Thus we need to do some division to get back to us.
      */
     Linux::UDelayEvent *constUDelaySkipEvent;
+
+    /** These variables store addresses of important data structures
+     * that are normaly kept coherent at boot with cache mainetence operations.
+     * Since these operations aren't supported in gem5, we keep them coherent
+     * by making them uncacheable until all processors in the system boot.
+     */
+    Addr secDataPtrAddr;
+    Addr secDataAddr;
+    Addr penReleaseAddr;
 };
 
 #endif // __ARCH_ARM_LINUX_SYSTEM_HH__