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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-16 14:20:50 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 14:23:19 +0000 |
| commit | 20990ad5e9fc98b1fd5b107e8acad2fa97a4ef75 (patch) | |
| tree | 77e921a9d7ed9402789cb7c4602836f2a5e20d16 /src/arch/arm/miscregs.cc | |
| parent | e97a1fe390a91f30042d683ebc5e654d39844eda (diff) | |
| download | gem5-20990ad5e9fc98b1fd5b107e8acad2fa97a4ef75.tar.xz | |
arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL
Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 7283b205f..87cc3fde3 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1117,7 +1117,7 @@ canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; - switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { + switch (currEL(cpsr)) { case EL0: return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : miscRegInfo[reg][MISCREG_USR_NS_RD]; @@ -1140,7 +1140,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) // Check for SP_EL0 access while SPSEL == 0 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) return false; - ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); + ExceptionLevel el = currEL(cpsr); if (reg == MISCREG_DAIF) { SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); if (el == EL0 && !sctlr.uma) |