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| author | Dam Sunwoo <dam.sunwoo@arm.com> | 2014-08-13 06:57:36 -0400 |
|---|---|---|
| committer | Dam Sunwoo <dam.sunwoo@arm.com> | 2014-08-13 06:57:36 -0400 |
| commit | b04d6c7c33d779654c5a4fc614be4e20de2010c6 (patch) | |
| tree | 59ba7d5a64077f6bf68bc6832dd856a269034c7d /src/arch/arm/miscregs.cc | |
| parent | 74a4926fe0a92502ca98ca7656dca478d88eb2f1 (diff) | |
| download | gem5-b04d6c7c33d779654c5a4fc614be4e20de2010c6.tar.xz | |
arm: change MISCREG_L2ERRSR to warn not fail
Some newer binaries compiled for Versatile Express TC2 contain access
to implementation specific L2MERRSR registers. This causes an infinite
loop of undefined exceptions. This patch changes the behavior to "warn
not fail" to keep the workloads going.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 313ac18f9..4c950a643 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -770,7 +770,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = { // MISCREG_CPUMERRSR bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")), // MISCREG_L2MERRSR - bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")), + bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")), // AArch64 registers (Op0=2) // MISCREG_MDCCINT_EL1 @@ -1330,7 +1330,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = { // MISCREG_CPUMERRSR_EL1 bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")), // MISCREG_L2MERRSR_EL1 - bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")), + bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")), // MISCREG_CBAR_EL1 bitset<NUM_MISCREG_INFOS>(string("0101010101000000001")), |