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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-12-08 04:49:53 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-12-08 04:49:53 -0500 |
| commit | 9b7578d8c7f82e255776a354657d1f19f1ca64f4 (patch) | |
| tree | d79bb48d2611abf4b3142dbfad2c315a3c1d110e /src/arch/arm/miscregs.cc | |
| parent | 6a9fbd295d18d96b39f9d8ba6093bee17d318c1d (diff) | |
| download | gem5-9b7578d8c7f82e255776a354657d1f19f1ca64f4.tar.xz | |
arm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0
The aarch64 system register decoder is currently not decoding
PMXEVTYPER_EL0 and PMCCFILTR_EL0 correctly. This changeset updates the
decoder so that they are decoded using the values in table C5-6 in ARM
DDI 0478A.c.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index d8c257f08..2ad256273 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -3177,7 +3177,7 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, case 0: return MISCREG_PMCCNTR_EL0; case 1: - return MISCREG_PMCCFILTR_EL0; + return MISCREG_PMXEVTYPER_EL0; case 2: return MISCREG_PMXEVCNTR_EL0; } @@ -3434,6 +3434,11 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_PMEVTYPER5_EL0; } break; + case 15: + switch (op2) { + case 7: + return MISCREG_PMCCFILTR_EL0; + } } break; case 4: |