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| author | Matt Horsnell <Matt.Horsnell@ARM.com> | 2011-01-18 16:30:05 -0600 |
|---|---|---|
| committer | Matt Horsnell <Matt.Horsnell@ARM.com> | 2011-01-18 16:30:05 -0600 |
| commit | adbd84ab9fffdcdce18f564acffa508c10164c9f (patch) | |
| tree | aa6d90545a22e3524e33022176666569a47d83ba /src/arch/arm/miscregs.cc | |
| parent | 11bef2ab3811e5c7a65d33ba86718d8c606be87a (diff) | |
| download | gem5-adbd84ab9fffdcdce18f564acffa508c10164c9f.tar.xz | |
ARM: The ARM decoder should not panic when decoding undefined holes is arch.
This can abort simulations when the fetch unit runs ahead and speculatively
decodes instructions that are off the execution path.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index fd861befc..13dec0add 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -451,8 +451,6 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) // Implementation defined break; } - warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n", - crn, opc1, crm, opc2); // Unrecognized register return NUM_MISCREGS; } |