arch-arm: IMPLEMENTATION DEFINED register

A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.

Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7922
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 19 insertions, 2 deletions

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index c0b6aa5d5..7d5441ca8 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -502,6 +502,19 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         }
         break;
       case 9:
+        // Every cop register with CRn = 9 and CRm in
+        // {0-2}, {5-8} is implementation defined regardless
+        // of opc1 and opc2.
+        switch (crm) {
+          case 0:
+          case 1:
+          case 2:
+          case 5:
+          case 6:
+          case 7:
+          case 8:
+            return MISCREG_IMPDEF_UNIMPL;
+        }
         if (opc1 == 0) {
             switch (crm) {
               case 12:
@@ -565,7 +578,9 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
       case 10:
         if (opc1 == 0) {
             // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
-            if (crm == 2) { // TEX Remap Registers
+            if (crm < 2) {
+                return MISCREG_IMPDEF_UNIMPL;
+            } else if (crm == 2) { // TEX Remap Registers
                 if (opc2 == 0) {
                     // Selector is TTBCR.EAE
                     return MISCREG_PRRR_MAIR0;
@@ -609,6 +624,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
               case 8:
               case 15:
                 // Reserved for DMA operations for TCM access
+                return MISCREG_IMPDEF_UNIMPL;
+              default:
                 break;
             }
         }
@@ -689,7 +706,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         break;
       case 15:
         // Implementation defined
-        return MISCREG_CP15_UNIMPL;
+        return MISCREG_IMPDEF_UNIMPL;
     }
     // Unrecognized register
     return MISCREG_CP15_UNIMPL;