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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | cb9936cfdefdebf2c0b950f93a62d504d356524d (patch) | |
| tree | 3280784b875ccd23475c3f08edc774b50ef1c97d /src/arch/arm/miscregs.cc | |
| parent | f246be4cbc27b4173f6917b430a31b9a39cdb380 (diff) | |
| download | gem5-cb9936cfdefdebf2c0b950f93a62d504d356524d.tar.xz | |
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index aedc0fce5..e4375fb8a 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -38,6 +38,7 @@ */ #include "arch/arm/miscregs.hh" +#include "base/misc.hh" namespace ArmISA { @@ -424,6 +425,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) // Implementation defined break; } + warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n", + crn, opc1, crm, opc2); // Unrecognized register return NUM_MISCREGS; } |